 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| freescale semiconductor data sheet: technical data document number: mpc5606b rev. 3, 9/2013 ? freescale semiconductor, inc., 2011?2013. all rights reserved. MPC5606BK 100 lqfp 14 mm x 14 mm 144 lqfp 20 mm x 20 mm 176 lqfp 24 mm x 24 mm 1 introduction 1.1 document overview this document describes the f eatures of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. 1.2 description this family of 32-bit system-on-chip (soc) microcontrollers is the latest achievement in integrated automotive application controllers. it belongs to an expanding family of automotive-focused products de signed to address the next wave of body electronics applications within the vehicle. the advanced and cost-efficient e200z0 host processor core of this automotive controller family complies with the power architecture ? technology and only implements the vle (variable-length encoding) apu (auxiliary processor unit), providing improved code density. it operates at speeds of up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of current powe r architecture devices and is supported with software drivers, operating systems and configuration co de to assist with users implementations. qorivva MPC5606BK microcontroller data sheet 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . 4 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . 27 3.4 recommended operating conditions . . . . . . . . . . . . . . . 28 3.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.6 i/o pad electrical characteristics . . . . . . . . . . . . . . . . . . 33 3.7 reset electrical characteristics . . . . . . . . . . . . . . . . . . 45 3.8 power management electrical characteristics . . . . . . . . 48 3.9 power consumption in different application modes . . . . 53 3.10 flash memory electrical characteristics . . . . . . . . . . . . . 54 3.11 electromagnetic compatibility (emc) characteristics . . . 56 3.12 fast external crystal oscill ator (4 to 16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.13 slow external crystal osci llator (32 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.14 fmpll electrical characteristics. . . . . . . . . . . . . . . . . . . 63 3.15 fast internal rc oscillator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.16 slow internal rc oscill ator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.17 adc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 66 3.18 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.1 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . 86 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
MPC5606BK microcontroller data sheet, rev. 3 2 freescale semiconductor 1.3 device comparison table 1 summarizes the functions of the blocks present on the MPC5606BK. table 1. MPC5606BK family comparison 1 1 feature set dependent on selected peripheral multiplexing; table shows example. feature mpc5605bk MPC5606BK package 100 lqfp 144 lqfp 176 lqfp 100 lqfp 144 lqfp 176 lqfp cpu e200z0h execution speed 2 2 based on 125 ? c ambient operating temperature. up to 64 mhz code flash memory 768 kb 1 mb data flash memory 64 (4 x 16) kb sram 64 kb 80 kb mpu 8-entry edma 16 ch 10-bit adc yes dedicated 3 3 not shared with 12-bit adc, but possibly shared with other alternate functions. 7ch 15ch 29ch 7ch 15ch 29ch shared with 12-bit adc 19 ch 12-bit adc yes dedicated 4 4 not shared with 10-bit adc, but possibly shared with other alternate functions. 5 ch shared with 10-bit adc 19 ch total timer i/o 5 emios 5 refer to emios section of device reference manual for information on the channel configuration and functions. 37 ch, 16-bit 64 ch, 16-bit 37 ch, 16-bit 64 ch, 16-bit counter / opwm / icoc 6 6 each channel supports a range of modes including modulus counters, pwm generation, input capture, output compare. 10 ch o(i)pwm / opwfmb / opwmcb / icoc 7 7 each channel supports a range of modes including pwm gen eration with dead time, input capture, output compare. 7ch o(i)pwm / icoc 8 8 each channel supports a range of modes including pwm generation, input capture, output compare, period and pulse width measurement. 7ch 14ch opwm / icoc 9 9 each channel supports a range of modes including pwm generation, input capture, and output compare. 13 ch 33 ch sci (linflex) 468468 spi (dspi) 356356 can (flexcan) 6 i 2 c 1 32 khz oscillator yes gpio 10 10 maximum i/o count based on multiplexing with peripherals. 77 121 149 77 121 149 debug jtag MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 3 1.4 block diagram figure 1 shows a top-level block diagram of the MPC5606BK. figure 1. MPC5606BK block diagram 6 x dspi fmpll sram siul reset control 80 kb external imux gpio & jtag pad control jtag port e200z0h interrupt requests 64-bit 3 3 crossbar switch 6 x flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siul . . . intc i 2 c . . . 8 x linflex 64 ch 29 ch 10-bit mpu cmu sram flash memory code flash 1.0 mb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module flexcan controller area network cflash code flash memory cmu clock monitor unit ctu cross triggering unit dflash data flash memory dspi deserial serial peripheral interface edma enhanced direct memory access emios enhanced modular input output system fmpll frequency-modulated phase-locked loop i 2 c inter-integrated circuit bus imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) mc_cgm clock generation module mc_me mode entry module mpu memory protection unit nmi non-maskable interrupt mc_pcu power control unit mc_rgm reset generation module pit periodic interrupt timer rtc real-time clock siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer wkpu wakeup unit mpu ecsm from peripheral registers blocks adc emios 19 ch 10-bit/12-bit adc (master) . . . . . . . . . wkpu 5 ch 12-bit adc edma interrupt request with wakeup functionality MPC5606BK microcontroller data sheet, rev. 3 4 freescale semiconductor 2 package pinouts and signal descriptions 2.1 package pinouts the available lqfp pinouts are provid ed in the following figures. for pin signal descriptions, please see table 2 . figure 2 shows the MPC5606BK in the 176 lqfp package. figure 2. 176 lqfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pa [ 1 1 ] pa [ 1 0 ] pa [ 9 ] pa [ 8 ] pa [ 7 ] pe[13] pf[14] pf[15] vdd_hv vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa [ 3 ] pi[13] pi[12] pi[11] pi[10] pi[9] pi[8] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] vdd_hv_adc1 vss_hv_adc1 pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pb[3] pc[9] pc[14] pc[15] pj[4] vdd_hv vss_hv ph[15] ph[13] ph[14] pi[6] pi[7] pg[5] pg[4] pg[3] pg[2] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pj[3] pj[2] pj[1] pj[0] pi[15] pi[14] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] vdd_hv vss_hv pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pi[0] pi[1] pi[2] pi[3] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pi[4] pi[5] ph[12] ph[11] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] 176 lqfp top view MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 5 figure 3 shows the MPC5606BK in the 144 lqfp package. figure 3. 144 lqfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pb[3] pc[9] pc[14] pc[15] pg[5] pg[4] pg[3] pg[2] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] pa[11] pa[10] pa [ 9 ] pa [ 8 ] pa [ 7 ] pe[13] pf[14] pf[15] vdd_hv vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] vdd_hv_adc1 vss_hv_adc1 pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pc[7] pf[10] pf[11] pa [ 1 5 ] pf[13] pa [ 1 4 ] pa [ 4 ] pa [ 1 3 ] pa [ 1 2 ] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] 144 lqfp top view MPC5606BK microcontroller data sheet, rev. 3 6 freescale semiconductor figure 4 shows the MPC5606BK in the 100 lqfp package. figure 4. 100 lqfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pb[3] pc[9] pc[14] pc[15] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[11] pc[10] pb[0] pb[1] pc[6] pa [ 1 1 ] pa [ 1 0 ] pa [ 9 ] pa [ 8 ] pa [ 7 ] vdd_hv vss_hv pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] vdd_hv_adc1 vss_hv_adc1 pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pc[7] pa[15] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pe[12] 100 lqfp top view MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 7 2.2 pin muxing table 2 defines the pin list and muxing for this device. each entry of table 2 shows all the possible configura tions for each pin, via the altern ate functions. the default function assigned to each pin after reset is indicated by af0. table 2. functional port pins port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp port a pa[0] pcr[0] af0 af1 af2 af3 ? gpio[0] e0uc[0] clkout e0uc[13] wkup[19] 4 siul emios_0 mc_cgm emios_0 wkup i/o i/o o i/o i mtristate121624 pa[1] pcr[1] af0 af1 af2 af3 ? gpio[1] e0uc[1] nmi 5 ? wkup[2] 4 siul emios_0 wkup ? wkup i/o i/o i ? i s tristate 7 11 19 pa[2] pcr[2] af0 af1 af2 af3 ? gpio[2] e0uc[2] ? ma[2] wkup[3] 4 siul emios_0 ? adc_0 wkup i/o i/o ? o i s tristate 5 9 17 pa[3] pcr[3] af0 af1 af2 af3 ? ? gpio[3] e0uc[3] lin5tx cs4_1 eirq[0] adc1_s[0] siul emios_0 linflex_5 dspi_1 siul adc_1 i/o i/o o o i i j tristate 68 90 114 pa[4] pcr[4] af0 af1 af2 af3 ? ? gpio[4] e0uc[4] ? cs0_1 lin5rx wkup[9] 4 siul emios_0 ? dspi_1 linflex_5 wkup i/o i/o ? i/o i i stristate294351 pa[5] pcr[5] af0 af1 af2 af3 gpio[5] e0uc[5] lin4tx ? siul emios_0 linflex_4 ? i/o i/o o ? m tristate 79 118 146 pa[6] pcr[6] af0 af1 af2 af3 ? ? gpio[6] e0uc[6] ? cs1_1 eirq[1] lin4rx siul emios_0 ? dspi_1 siul linflex_4 i/o i/o ? o i i s tristate 80 119 147 MPC5606BK microcontroller data sheet, rev. 3 8 freescale semiconductor pa[7] pcr[7] af0 af1 af2 af3 ? ? gpio[7] e0uc[7] lin3tx ? eirq[2] adc1_s[1] siul emios_0 linflex_3 ? siul adc_1 i/o i/o o ? i i j tristate 71 104 128 pa[8] pcr[8] af0 af1 af2 af3 ? n/a 6 ? gpio[8] e0uc[8] e0uc[14] ? eirq[3] abs[0] lin3rx siul emios_0 emios_0 ? siul bam linflex_3 i/o i/o i/o ? i i i s input, weak pull-up 72 105 129 pa[9] pcr[9] af0 af1 af2 af3 n/a 6 gpio[9] e0uc[9] ? cs2_1 fab siul emios_0 ? dspi_1 bam i/o i/o ? o i s pull- down 73 106 130 pa[10] pcr[10] af0 af1 af2 af3 ? gpio[10] e0uc[10] sda lin2tx adc1_s[2] siul emios_0 i 2 c_0 linflex_2 adc_1 i/o i/o i/o o i j tristate 74 107 131 pa[11] pcr[11] af0 af1 af2 af3 ? ? ? gpio[11] e0uc[11] scl ? eirq[16] lin2rx adc1_s[3] siul emios_0 i 2 c_0 ? siul linflex_2 adc_1 i/o i/o i/o ? i i i j tristate 75 108 132 pa[12] pcr[12] af0 af1 af2 af3 ? ? gpio[12] ? e0uc[28] cs3_1 eirq[17] sin_0 siul ? emios_0 dspi_1 siul dspi_0 i/o ? i/o o i i stristate314553 pa[13] pcr[13] af0 af1 af2 af3 gpio[13] sout_0 e0uc[29] ? siul dspi_0 emios_0 ? i/o o i/o ? mtristate304452 pa[14] pcr[14] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 e0uc[0] eirq[4] siul dspi_0 dspi_0 emios_0 siul i/o i/o i/o i/o i mtristate284250 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 9 pa[15] pcr[15] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 e0uc[1] wkup[10] 4 siul dspi_0 dspi_0 emios_0 wkup i/o i/o i/o i/o i mtristate274048 port b pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx e0uc[30] lin0tx siul flexcan_0 emios_0 linflex_0 i/o o i/o o mtristate233139 pb[1] pcr[17] af0 af1 af2 af3 ? ? ? gpio[17] ? e0uc[31] ? wkup[4] 4 can0rx lin0rx siul ? emios_0 ? wkup flexcan_0 linflex_0 i/o ? i/o ? i i i stristate243240 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx sda e0uc[30] siul linflex_0 i 2 c_0 emios_0 i/o o i/o i/o m tristate 100 144 176 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] e0uc[31] scl ? wkup[11] 4 lin0rx siul emios_0 i 2 c_0 ? wkup linflex_0 i/o i/o i/o ? i i stristate111 pb[4] pcr[20] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[0] adc1_p[0] gpio[20] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate507288 pb[5] pcr[21] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[1] adc1_p[1] gpio[21] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate537591 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 10 freescale semiconductor pb[6] pcr[22] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[2] adc1_p[2] gpio[22] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate547692 pb[7] pcr[23] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[3] adc1_p[3] gpio[23] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate557793 pb[8] pcr[24] af0 af1 af2 af3 ? ? ? ? gpio[24] ? ? ? osc32k_xtal 7 wkup[25] adc0_s[0] adc1_s[4] siul ? ? ? osc32k wkup adc_0 adc_1 i ? ? ? ? i i i i ? 39 53 61 pb[9] pcr[25] af0 af1 af2 af3 ? ? ? ? gpio[25] ? ? ? osc32k_extal 7 wkup[26] adc0_s[1] adc1_s[5] siul ? ? ? osc32k wkup adc_0 adc_1 i ? ? ? ? i i i i ? 38 52 60 pb[10] pcr[26] af0 af1 af2 af3 ? ? ? gpio[26] ? ? ? wkup[8] 4 adc0_s[2] adc1_s[6] siul ? ? ? wkup adc_0 adc_1 i/o ? ? ? i i i jtristate405462 pb[11] pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 adc0_s[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? i/o i j tristate ? ? 97 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 adc0_x[0] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 61 83 101 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 11 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 adc0_x[1] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 63 85 103 pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 adc0_x[2] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 65 87 105 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 adc0_x[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 67 89 107 port c pc[0] 8 pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m input, weak pull-up 87 126 154 pc[1] 8 pcr[33] af0 af1 af2 af3 gpio[33] ? tdo ? siul ? jtagc ? i/o ? o ? f 9 tristate 82 121 149 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 can4tx debug[0] eirq[5] siul dspi_1 flexcan_4 sscm siul i/o i/o o o i m tristate 78 117 145 pc[3] pcr[35] af0 af1 af2 af3 ? ? ? gpio[35] cs0_1 ma[0] debug[1] eirq[6] can1rx can4rx siul dspi_1 adc_0 sscm siul flexcan_1 flexcan_4 i/o i/o o o i i i s tristate 77 116 144 pc[4] pcr[36] af0 af1 af2 af3 ? ? ? gpio[36] e1uc[31] ? debug[2] eirq[18] sin_1 can3rx siul emios_1 ? sscm siul dspi_1 flexcan_3 i/o i/o ? o i i i m tristate 92 131 159 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 12 freescale semiconductor pc[5] pcr[37] af0 af1 af2 af3 ? gpio[37] sout_1 can3tx debug[3] eirq[7] siul dspi_1 flexcan_3 sscm siul i/o o o o i m tristate 91 130 158 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx e1uc[28] debug[4] siul linflex_1 emios_1 sscm i/o o i/o o stristate253644 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? e1uc[29] debug[5] lin1rx wkup[12] 4 siul ? emios_1 sscm linflex_1 wkup i/o ? i/o o i i stristate263745 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx e0uc[3] debug[6] siul linflex_2 emios_0 sscm i/o o i/o o s tristate 99 143 175 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? e0uc[7] debug[7] wkup[13] 4 lin2rx siul ? emios_0 sscm wkup linflex_2 i/o ? i/o o i i stristate222 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] can1tx can4tx ma[1] siul flexcan_1 flexcan_4 adc_0 i/o o o o mtristate222836 pc[11] pcr[43] af0 af1 af2 af3 ? ? ? gpio[43] ? ? ma[2] wkup[5] 4 can1rx can4rx siul ? ? adc_0 wkup flexcan_1 flexcan_4 i/o ? ? o i i i stristate212735 pc[12] pcr[44] af0 af1 af2 af3 ? ? gpio[44] e0uc[12] ? ? eirq[19] sin_2 siul emios_0 ? ? siul dspi_2 i/o i/o ? ? i i m tristate 97 141 173 pc[13] pcr[45] af0 af1 af2 af3 gpio[45] e0uc[13] sout_2 ? siul emios_0 dspi_2 ? i/o i/o o ? s tristate 98 142 174 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 13 pc[14] pcr[46] af0 af1 af2 af3 ? gpio[46] e0uc[14] sck_2 ? eirq[8] siul emios_0 dspi_2 ? siul i/o i/o i/o ? i stristate333 pc[15] pcr[47] af0 af1 af2 af3 ? gpio[47] e0uc[15] cs0_2 ? eirq[20] siul emios_0 dspi_2 ? siul i/o i/o i/o ? i mtristate444 port d pd[0] pcr[48] af0 af1 af2 af3 ? ? ? gpio[48] ? ? ? wkup[27] adc0_p[4] adc1_p[4] siul ? ? ? wkup adc_0 adc_1 i ? ? ? i i i itristate416377 pd[1] pcr[49] af0 af1 af2 af3 ? ? ? gpio[49] ? ? ? wkup[28] adc0_p[5] adc1_p[5] siul ? ? ? wkup adc_0 adc_1 i ? ? ? i i i itristate426478 pd[2] pcr[50] af0 af1 af2 af3 ? ? gpio[50] ? ? ? adc0_p[6] adc1_p[6] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate436579 pd[3] pcr[51] af0 af1 af2 af3 ? ? gpio[51] ? ? ? adc0_p[7] adc1_p[7] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate446680 pd[4] pcr[52] af0 af1 af2 af3 ? ? gpio[52] ? ? ? adc0_p[8] adc1_p[8] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate456781 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 14 freescale semiconductor pd[5] pcr[53] af0 af1 af2 af3 ? ? gpio[53] ? ? ? adc0_p[9] adc1_p[9] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate466882 pd[6] pcr[54] af0 af1 af2 af3 ? ? gpio[54] ? ? ? adc0_p[10] adc1_p[10] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate476983 pd[7] pcr[55] af0 af1 af2 af3 ? ? gpio[55] ? ? ? adc0_p[11] adc1_p[11] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate487084 pd[8] pcr[56] af0 af1 af2 af3 ? ? gpio[56] ? ? ? adc0_p[12] adc1_p[12] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate497187 pd[9] pcr[57] af0 af1 af2 af3 ? ? gpio[57] ? ? ? adc0_p[13] adc1_p[13] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate567894 pd[10] pcr[58] af0 af1 af2 af3 ? ? gpio[58] ? ? ? adc0_p[14] adc1_p[14] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate577995 pd[11] pcr[59] af0 af1 af2 af3 ? ? gpio[59] ? ? ? adc0_p[15] adc1_p[15] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate588096 pd[12] pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? adc0_s[4] siul dspi_0 emios_0 ? adc_0 i/o o i/o ? i j tristate ? ? 100 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 15 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? adc0_s[5] siul dspi_1 emios_0 ? adc_0 i/o i/o i/o ? i j tristate 62 84 102 pd[14] pcr[62] af0 af1 af2 af3 ? gpio[62] cs1_1 e0uc[26] ? adc0_s[6] siul dspi_1 emios_0 ? adc_0 i/o o i/o ? i j tristate 64 86 104 pd[15] pcr[63] af0 af1 af2 af3 ? gpio[63] cs2_1 e0uc[27] ? adc0_s[7] siul dspi_1 emios_0 ? adc_0 i/o o i/o ? i j tristate 66 88 106 port e pe[0] pcr[64] af0 af1 af2 af3 ? ? gpio[64] e0uc[16] ? ? wkup[6] 4 can5rx siul emios_0 ? ? wkup flexcan_5 i/o i/o ? ? i i s tristate 6 10 18 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] can5tx ? siul emios_0 flexcan_5 ? i/o i/o o ? m tristate 8 12 20 pe[2] pcr[66] af0 af1 af2 af3 ? ? gpio[66] e0uc[18] ? ? eirq[21] sin_1 siul emios_0 ? ? siul dspi_1 i/o i/o ? ? i i m tristate 89 128 156 pe[3] pcr[67] af0 af1 af2 af3 gpio[67] e0uc[19] sout_1 ? siul emios_0 dspi_1 ? i/o i/o o ? m tristate 90 129 157 pe[4] pcr[68] af0 af1 af2 af3 ? gpio[68] e0uc[20] sck_1 ? eirq[9] siul emios_0 dspi_1 ? siul i/o i/o i/o ? i m tristate 93 132 160 pe[5] pcr[69] af0 af1 af2 af3 gpio[69] e0uc[21] cs0_1 ma[2] siul emios_0 dspi_1 adc_0 i/o i/o i/o o m tristate 94 133 161 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 16 freescale semiconductor pe[6] pcr[70] af0 af1 af2 af3 ? gpio[70] e0uc[22] cs3_0 ma[1] eirq[22] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m tristate 95 139 167 pe[7] pcr[71] af0 af1 af2 af3 ? gpio[71] e0uc[23] cs2_0 ma[0] eirq[23] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m tristate 96 140 168 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] can2tx e0uc[22] can3tx siul flexcan_2 emios_0 flexcan_3 i/o o i/o o m tristate 9 13 21 pe[9] pcr[73] af0 af1 af2 af3 ? ? ? gpio[73] ? e0uc[23] ? wkup[7] 4 can2rx can3rx siul ? emios_0 ? wkup flexcan_2 flexcan_3 i/o ? i/o ? i i i stristate101422 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] lin3tx cs3_1 e1uc[30] eirq[10] siul linflex_3 dspi_1 emios_1 siul i/o o o i/o i stristate111523 pe[11] pcr[75] af0 af1 af2 af3 ? ? gpio[75] e0uc[24] cs4_1 ? lin3rx wkup[14] 4 siul emios_0 dspi_1 ? linflex_3 wkup i/o i/o o ? i i stristate131725 pe[12] pcr[76] af0 af1 af2 af3 ? ? ? gpio[76] ? e1uc[19] 10 ? eirq[11] sin_2 adc1_s[7] siul ? emios_1 ? siul dspi_2 adc_1 i/o ? i/o ? i i i j tristate 76 109 133 pe[13] pcr[77] af0 af1 af2 af3 gpio[77] sout_2 e1uc[20] ? siul dspi_2 emios_1 ? i/o o i/o ? s tristate ? 103 127 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 17 pe[14] pcr[78] af0 af1 af2 af3 ? gpio[78] sck_2 e1uc[21] ? eirq[12] siul dspi_2 emios_1 ? siul i/o i/o i/o ? i s tristate ? 112 136 pe[15] pcr[79] af0 af1 af2 af3 gpio[79] cs0_2 e1uc[22] ? siul dspi_2 emios_1 ? i/o i/o i/o ? m tristate ? 113 137 port f pf[0] pcr[80] af0 af1 af2 af3 ? gpio[80] e0uc[10] cs3_1 ? adc0_s[8] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i j tristate ? 55 63 pf[1] pcr[81] af0 af1 af2 af3 ? gpio[81] e0uc[11] cs4_1 ? adc0_s[9] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i j tristate ? 56 64 pf[2] pcr[82] af0 af1 af2 af3 ? gpio[82] e0uc[12] cs0_2 ? adc0_s[10] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 57 65 pf[3] pcr[83] af0 af1 af2 af3 ? gpio[83] e0uc[13] cs1_2 ? adc0_s[11] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 58 66 pf[4] pcr[84] af0 af1 af2 af3 ? gpio[84] e0uc[14] cs2_2 ? adc0_s[12] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 59 67 pf[5] pcr[85] af0 af1 af2 af3 ? gpio[85] e0uc[22] cs3_2 ? adc0_s[13] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 60 68 pf[6] pcr[86] af0 af1 af2 af3 ? gpio[86] e0uc[23] cs1_1 ? adc0_s[14] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i j tristate ? 61 69 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 18 freescale semiconductor pf[7] pcr[87] af0 af1 af2 af3 ? gpio[87] ? cs2_1 ? adc0_s[15] siul ? dspi_1 ? adc_0 i/o ? o ? i j tristate ? 62 70 pf[8] pcr[88] af0 af1 af2 af3 gpio[88] can3tx cs4_0 can2tx siul flexcan_3 dspi_0 flexcan_2 i/o o o o m tristate ? 34 42 pf[9] pcr[89] af0 af1 af2 af3 ? ? ? gpio[89] e1uc[1] cs5_0 ? wkup[22] 4 can2rx can3rx siul emios_1 dspi_0 ? wkup flexcan_2 flexcan_3 i/o i/o o ? i i i s tristate ? 33 41 pf[10] pcr[90] af0 af1 af2 af3 gpio[90] cs1_0 lin4tx e1uc[2] siul dspi_0 linflex_4 emios_1 i/o o o i/o m tristate ? 38 46 pf[11] pcr[91] af0 af1 af2 af3 ? ? gpio[91] cs2_0 e1uc[3] ? wkup[15] 4 lin4rx siul dspi_0 emios_1 ? wkup linflex_4 i/o o i/o ? i i s tristate ? 39 47 pf[12] pcr[92] af0 af1 af2 af3 gpio[92] e1uc[25] lin5tx ? siul emios_1 linflex_5 ? i/o i/o o ? m tristate ? 35 43 pf[13] pcr[93] af0 af1 af2 af3 ? ? gpio[93] e1uc[26] ? ? wkup[16] 4 lin5rx siul emios_1 ? ? wkup linflex_5 i/o i/o ? ? i i s tristate ? 41 49 pf[14] pcr[94] af0 af1 af2 af3 gpio[94] can4tx e1uc[27] can1tx siul flexcan_4 emios_1 flexcan_1 i/o o i/o o m tristate ? 102 126 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 19 pf[15] pcr[95] af0 af1 af2 af3 ? ? ? gpio[95] e1uc[4] ? ? eirq[13] can1rx can4rx siul emios_1 ? ? siul flexcan_1 flexcan_4 i/o i/o ? ? i i i s tristate ? 101 125 port g pg[0] pcr[96] af0 af1 af2 af3 gpio[96] can5tx e1uc[23] ? siul flexcan_5 emios_1 ? i/o o i/o ? m tristate ? 98 122 pg[1] pcr[97] af0 af1 af2 af3 ? ? gpio[97] ? e1uc[24] ? eirq[14] can5rx siul ? emios_1 ? siul flexcan_5 i/o ? i/o ? i i s tristate ? 97 121 pg[2] pcr[98] af0 af1 af2 af3 gpio[98] e1uc[11] sout_3 ? siul emios_1 dspi_3 ? i/o i/o o ? m tristate ? 8 16 pg[3] pcr[99] af0 af1 af2 af3 ? gpio[99] e1uc[12] cs0_3 ? wkup[17] 4 siul emios_1 dspi_3 ? wkup i/o i/o o ? i s tristate ? 7 15 pg[4] pcr[100] af0 af1 af2 af3 gpio[100] e1uc[13] sck_3 ? siul emios_1 dspi_3 ? i/o i/o i/o ? m tristate ? 6 14 pg[5] pcr[101] af0 af1 af2 af3 ? ? gpio[101] e1uc[14] ? ? wkup[18] 4 sin_3 siul emios_1 ? ? wkup dspi_3 i/o i/o ? ? i i s tristate ? 5 13 pg[6] pcr[102] af0 af1 af2 af3 gpio[102] e1uc[15] lin6tx ? siul emios_1 linflex_6 ? i/o i/o o ? m tristate ? 30 38 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 20 freescale semiconductor pg[7] pcr[103] af0 af1 af2 af3 ? ? gpio[103] e1uc[16] e1uc[30] ? wkup[20] 4 lin6rx siul emios_1 emios_1 ? wkup linflex_6 i/o i/o i/o ? i i s tristate ? 29 37 pg[8] pcr[104] af0 af1 af2 af3 ? gpio[104] e1uc[17] lin7tx cs0_2 eirq[15] siul emios_1 linflex_7 dspi_2 siul i/o i/o o i/o i s tristate ? 26 34 pg[9] pcr[105] af0 af1 af2 af3 ? ? gpio[105] e1uc[18] ? sck_2 wkup[21] 4 lin7rx siul emios_1 ? dspi_2 wkup linflex_7 i/o i/o ? i/o i i s tristate ? 25 33 pg[10] pcr[106] af0 af1 af2 af3 ? gpio[106] e0uc[24] e1uc[31] ? sin_4 siul emios_0 emios_1 ? dspi_4 i/o i/o i/o ? i s tristate ? 114 138 pg[11] pcr[107] af0 af1 af2 af3 gpio[107] e0uc[25] cs0_4 ? siul emios_0 dspi_4 ? i/o i/o o ? m tristate ? 115 139 pg[12] pcr[108] af0 af1 af2 af3 gpio[108] e0uc[26] sout_4 ? siul emios_0 dspi_4 ? i/o i/o o ? m tristate ? 92 116 pg[13] pcr[109] af0 af1 af2 af3 gpio[109] e0uc[27] sck_4 ? siul emios_0 dspi_4 ? i/o i/o i/o ? m tristate ? 91 115 pg[14] pcr[110] af0 af1 af2 af3 gpio[110] e1uc[0] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? 110 134 pg[15] pcr[111] af0 af1 af2 af3 ? gpio[111] e1uc[1] ? ? ? siul emios_1 ? ? ? i/o i/o ? ? ? m tristate ? 111 135 port h table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 21 ph[0] pcr[112] af0 af1 af2 af3 ? gpio[112] e1uc[2] ? ? sin_1 siul emios_1 ? ? dspi_1 i/o i/o ? ? i m tristate ? 93 117 ph[1] pcr[113] af0 af1 af2 af3 gpio[113] e1uc[3] sout_1 ? siul emios_1 dspi_1 ? i/o i/o o ? m tristate ? 94 118 ph[2] pcr[114] af0 af1 af2 af3 gpio[114] e1uc[4] sck_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? 95 119 ph[3] pcr[115] af0 af1 af2 af3 gpio[115] e1uc[5] cs0_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? 96 120 ph[4] pcr[116] af0 af1 af2 af3 gpio[116] e1uc[6] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? 134 162 ph[5] pcr[117] af0 af1 af2 af3 gpio[117] e1uc[7] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? 135 163 ph[6] pcr[118] af0 af1 af2 af3 gpio[118] e1uc[8] ? ma[2] siul emios_1 ? adc_0 i/o i/o ? o m tristate ? 136 164 ph[7] pcr[119] af0 af1 af2 af3 gpio[119] e1uc[9] cs3_2 ma[1] siul emios_1 dspi_2 adc_0 i/o i/o o o m tristate ? 137 165 ph[8] pcr[120] af0 af1 af2 af3 gpio[120] e1uc[10] cs2_2 ma[0] siul emios_1 dspi_2 adc_0 i/o i/o o o m tristate ? 138 166 ph[9] 8 pcr[121] af0 af1 af2 af3 gpio[121] ? tck ? siul ? jtagc ? i/o ? i ? s input, weak pull-up 88 127 155 ph[10] 8 pcr[122] af0 af1 af2 af3 gpio[122] ? tms ? siul ? jtagc ? i/o ? i ? m input, weak pull-up 81 120 148 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 22 freescale semiconductor ph[11] pcr[123] af0 af1 af2 af3 gpio[123] sout_3 cs0_4 e1uc[5] siul dspi_3 dspi_4 emios_1 i/o o i/o i/o m tristate ? ? 140 ph[12] pcr[124] af0 af1 af2 af3 gpio[124] sck_3 cs1_4 e1uc[25] siul dspi_3 dspi_4 emios_1 i/o i/o i/o ? m tristate ? ? 141 ph[13] pcr[125] af0 af1 af2 af3 gpio[125] sout_4 cs0_3 e1uc[26] siul dspi_4 dspi_3 emios_1 i/o o i/o ? mtristate ? ? 9 ph[14] pcr[126] af0 af1 af2 af3 gpio[126] sck_4 cs1_3 e1uc[27] siul dspi_4 dspi_3 emios_1 i/o i/o i/o ? m tristate ? ? 10 ph[15] pcr[127] af0 af1 af2 af3 gpio[127] sout_5 ? e1uc[17] siul dspi_5 ? emios_1 i/o o ? ? mtristate ? ? 8 port i pi[0] pcr[128] af0 af1 af2 af3 gpio[128] e0uc[28] ? ? siul emios_0 ? ? i/o i/o ? ? s tristate ? ? 172 pi[1] pcr[129] af0 af1 af2 af3 ? ? gpio[129] e0uc[29] ? ? wkup[24] 4 ? siul emios_0 ? ? wkup ? i/o i/o ? ? i ? s tristate ? ? 171 pi[2] pcr[130] af0 af1 af2 af3 gpio[130] e0uc[30] ? ? siul emios_0 ? ? i/o i/o ? ? s tristate ? ? 170 pi[3] pcr[131] af0 af1 af2 af3 ? ? gpio[131] e0uc[31] ? ? wkup[23] 4 ? siul emios_0 ? ? wkup ? i/o i/o ? ? i ? s tristate ? ? 169 pi[4] pcr[132] af0 af1 af2 af3 gpio[132] e1uc[28] sout_4 ? siul emios_1 dspi_4 ? i/o i/o o ? s tristate ? ? 143 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 23 pi[5] pcr[133] af0 af1 af2 af3 gpio[133] e1uc[29] sck_4 ? siul emios_1 dspi_4 ? i/o i/o i/o ? s tristate ? ? 142 pi[6] pcr[134] af0 af1 af2 af3 gpio[134] e1uc[30] cs0_4 ? siul emios_1 dspi_4 ? i/o i/o i/o ? s tristate ? ? 11 pi[7] pcr[135] af0 af1 af2 af3 gpio[135] e1uc[31] cs1_4 ? siul emios_1 dspi_4 ? i/o i/o i/o ? s tristate ? ? 12 pi[8] pcr[136] af0 af1 af2 af3 ? gpio[136] ? ? ? adc0_s[16] siul ? ? ? adc_0 i/o ? ? ? i j tristate ? ? 108 pi[9] pcr[137] af0 af1 af2 af3 ? gpio[137] ? ? ? adc0_s[17] siul ? ? ? adc_0 i/o ? ? ? i j tristate ? ? 109 pi[10] pcr[138] af0 af1 af2 af3 ? gpio[138] ? ? ? adc0_s[18] siul ? ? ? adc_0 i/o ? ? ? i j tristate ? ? 110 pi[11] pcr[139] af0 af1 af2 af3 ? ? gpio[139] ? ? ? adc0_s[19] sin_3 siul ? ? ? adc_0 dspi_3 i/o ? ? ? i i j tristate ? ? 111 pi[12] pcr[140] af0 af1 af2 af3 ? gpio[140] cs0_3 ? ? adc0_s[20] siul dspi_3 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 112 pi[13] pcr[141] af0 af1 af2 af3 ? gpio[141] cs1_3 ? ? adc0_s[21] siul dspi_3 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 113 table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 24 freescale semiconductor pi[14] pcr[142] af0 af1 af2 af3 ? ? gpio[142] ? ? ? adc0_s[22] sin_4 siul ? ? ? adc_0 dspi_4 i/o ? ? ? i i j tristate ? ? 76 pi[15] pcr[143] af0 af1 af2 af3 ? gpio[143] cs0_4 ? ? adc0_s[23] siul dspi_4 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 75 port j pj[0] pcr[144] af0 af1 af2 af3 ? gpio[144] cs1_4 ? ? adc0_s[24] siul dspi_4 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 74 pj[1] pcr[145] af0 af1 af2 af3 ? ? gpio[145] ? ? ? adc0_s[25] sin_5 siul ? ? ?? adc_0 dspi_5 i/o ? ? ? i i j tristate ? ? 73 pj[2] pcr[146] af0 af1 af2 af3 ? gpio[146] cs0_5 ? ? adc0_s[26] siul dspi_5 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 72 pj[3] pcr[147] af0 af1 af2 af3 ? gpio[147] cs1_5 ? ? adc0_s[27] siul dspi_5 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 71 pj[4] pcr[148] af0 af1 af2 af3 gpio[148] sck_5 e1uc[18] ? siul dspi_5 emios_1 ? i/o i/o ? ? mtristate ? ? 5 1 alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siul module. pcr.pa = 00 ? af0; pcr.pa = 01 ? af1; pcr.pa = 10 ? af2; pcr.pa = 11 ? af3. this is intended to select the output functions; to use one of the input f unctions, the pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 see ta b l e 3 . 3 the reset configuration applies during and after reset. table 2. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 25 3 electrical characteristics this section contains electrical char acteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to tak e precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent th e characteristics of the device and its demands on the system. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. 3.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 4 are used and the parameters are ta gged accordingly in the tables where appropriate. 4 all wkup pins also support external interrupt capability. see the wkpu chapter of the MPC5606BK microcontroller reference manual for further details. 5 nmi has higher priority than alternate function. wh en nmi is selected, the pcr.af field is ignored. 6 ?not applicable? because these functions are available on ly while the device is booting. see the bam chapter of the MPC5606BK microcontroller reference manual for details. 7 value of pcr.ibe bit must be 0. 8 out of reset all the functional pins except pc[0:1 ] and ph[9:10] are available to the user as gpio. pc[0:1] are available as jtag pins (tdi and tdo respectively). ph[9:10] are available as jtag pins (tck and tms respectively). it is up to the user to configur e these pins as gpio when needed. 9 pc[1] is a fast/medium pad but is in medium configuration by default. this pad is in alternate function 2 mode after reset which has tdo functionality. the reset value of pcr.obe is 1, but this setting has no impact as long as this pad stays in af2 mode. after configuring this pad as gpio (pcr.pa = 0), output buffer is enabled as reset value of pcr.obe = 1. 10 not available in 100lqfp package. table 3. pad types type description ffast i input only with analog feature j input/output with analog feature m medium sslow MPC5606BK microcontroller data sheet, rev. 3 26 freescale semiconductor note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.2 nvusro register portions of the device configuration, such as high voltage supp ly, oscillator margin, and watch dog enable/disable after reset a re controlled via bit values in the non-volatile user options register (nvusro) register. for a detailed description of the nv usro register, please refer to the MPC5606BK microcontroller reference manual . 3.2.1 nvusro[pad3v5v] field description table 5 shows how nvusro[pad3v5v] controls the device configuration. the dc electrical characteristics are dependent on the pad3v5v bit value. 3.2.2 nvusro[oscillator_margin] field description table 6 shows how nvusro[oscillator_margin] controls the device configuration. the fast external crystal oscillator consumptio n is dependent on the osci llator_margin bit value. table 4. paramete r classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. table 5. pad3v5v field description 1 1 see the MPC5606BK microcontro ller reference manual for more information on the nvusro register. value 2 2 the default manufacturing value is ?1?. this value can be programmed by the customer in shadow flash. description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 6. oscillator_margin field description 1 1 see the MPC5606BK microcontro ller reference manual for more information on the nvusro register. value 2 2 the default manufacturing value is ?1?. this value can be programmed by the customer in shadow flash. description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 27 3.2.3 nvusro[watchdog_en] field description the watchdog enable/disable confi guration after reset is dependent on the watchdog_en bit value. table 7 shows how nvusro[watchdog_en] c ontrols the device configuration. 3.3 absolute maximum ratings table 7. watchdog_en field description 1 1 see the MPC5606BK microcontro ller reference manual for more information on the nvusro register. value 2 2 the default manufacturing value is ?1?. this value can be programmed by the customer in shadow flash. description 0 disable after reset 1 enable after reset table 8. absolute maximum ratings symbol parameter conditions value unit min max v ss sr digital ground on vss_hv pins ? 0 0 v v dd sr voltage on vdd_hv pins with respect to ground (v ss ) ??0.36.0v v ss_lv sr voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss ) ?v ss ?0.1 v ss +0.1 v v dd_bv sr voltage on vdd_bv pin (regulator supply) with respect to ground (v ss ) ??0.36.0v relative to v dd ?0.3 v dd +0.3 v ss_adc sr voltage on vss_hv_adc0, vss_hv_adc1 (adc reference) pin with respect to ground (v ss ) ?v ss ?0.1 v ss +0.1 v v dd_adc sr voltage on vdd_hv_adc0, vdd_hv_adc1 (adc reference) with respect to ground (v ss ) ??0.36.0v relative to v dd v dd ? 0.3 v dd +0.3 v in sr voltage on any gpio pin with respect to ground (v ss ) ??0.36.0v relative to v dd ?v dd +0.3 i injpad sr injected input current on any pin during overload condition ? ?10 10 ma i injsum sr absolute sum of all injected input currents during overload condition ? ?50 50 i avgseg sr sum of all the static i/ o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ?70ma v dd = 3.3 v 10%, pad3v5v = 1 ?64 t storage sr storage temperature ? ?55 150 c MPC5606BK microcontroller data sheet, rev. 3 28 freescale semiconductor note stresses exceeding the recommended absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in MPC5606BK microcontroller data sheet, rev. 3 30 freescale semiconductor note ram data retention is guaranteed with v dd_lv not below 1.08 v. v dd_adc 5 sr voltage on vdd_hv_adc0, vdd_hv_adc1 (adc reference) with respect to ground (v ss ) ?4.55.5v voltage drop 2 3.0 5.5 relative to v dd v dd ? 0.1 v dd +0.1 v in sr voltage on any gpio pin with respect to ground (v ss ) ?v ss ? 0.1 ? v relative to v dd ?v dd +0.1 i injpad sr injected input current on any pin during overload condition ? ? 55ma i injsum sr absolute sum of all injected input currents during overload condition ? ? 50 50 tv dd sr v dd slope to ensure correct power up 6 ? ? 0.25 v/s t a c-grade part sr ambient temperature under bias f cpu < 64 mhz 7 ? 40 85 c t j c-grade part sr junction temperature under bias ? ? 40 110 t a v-grade part sr ambient temperature under bias f cpu < 64 mhz 7 ? 40 105 t j v-grade part sr junction temperature under bias ? ? 40 130 t a m-grade part sr ambient temperature under bias f cpu < 64 mhz 7 ? 40 125 t j m-grade part sr junction temperature under bias ? ? 40 150 1 100 nf capacitance needs to be provided between each v dd /v ss pair. 2 full device operation is guaranteed by design when the vo ltage drops below 4.5 v down to 3.0 v. however, certain analog electrical characteristics will not be guaranteed to stay wit hin the stated limits. 3 330 nf capacitance needs to be provided between each v dd_lv /v ss_lv supply pair. 4 470 nf capacitance needs to be provided between v dd_bv and the nearest v ss_lv (higher value may be needed depending on external regulator characteristics). while the supply voltage ramps up, the slope on v dd_bv should be less than 0.9v dd_hv in order to ensure the device does not enter regulator bypass mode. 5 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 6 guaranteed by device validation. please refer to section 3.5.1, external ballast resistor recommendations for minimum v dd slope to be guaranteed to ensure correct power up in case of external resistor usage. 7 this frequency includes the 4% frequency modulation guard band. table 10. recommended operating conditions (5.0 v) (continued) symbol parameter conditions value unit min max MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 31 3.5 thermal characteristics 3.5.1 external ballast r esistor recommendations external ballast resistor on v dd_bv pin helps in reducing the overall power dissipation inside the device. this resistor is required only when maximum power consumption exceeds the limit imposed by package thermal characteristics. as stated in table 11 lqfp thermal characteristics, cons idering a thermal resistance of 14 4 lqfp as 48.3 c/ w, at ambient temperature t a = 125 c, the junction temperature t j will cross 150 c if the total power dissipation is greater than (150 ? 125)/48.3 = 517 mw. theref ore, the total device current i ddmax at 125 c/5.5 v must not exceed 94.1 ma (i.e., pd/vdd). assuming an average i dd (v dd_hv ) of 15?20 ma consumption typically during device run mode, the lv domain consumption i dd (v dd_bv ) is thus limited to i ddmax ?i dd (v dd_hv ), i.e., 80 ma. therefore, respecting the maximum power allowed as explained in section 3.5.2, package thermal characteristics , it is recommended to use this resistor only in the 125 c/5 .5 v operating corner as pe r the following guidelines: ?if i dd (v dd_bv ) < 80 ma, then no resistor is required. ?if 80 ma < i dd (v dd_bv ) < 90 ma, then 4 ? resistor can be used. ?if i dd (v dd_bv ) > 90 ma, then 8 ? resistor can be used. using resistance in the range of 4?8 ? , the gain will be around 10?20% of total consumption on v dd_bv . for example, if 8 ? resistor is used, then power consumption when i dd (v dd_bv ) is 110 ma is equivalent to power consumption when i dd (v dd_bv ) is 90 ma (approximately) when resistor not used. in order to ensure correct power up, the minimum v dd_bv to be guaranteed is 30 ms/v. if the supply ramp is slower than this value, then lvdhv3b monitoring ballast supply v dd_bv pin gets triggered leading to device reset. until the supply reaches certain threshold, this low voltage monitor generates destruct ive reset event in the system. this threshold depends on the maximum i dd (v dd_bv ) possible across the external resistor. 3.5.2 package thermal characteristics table 11. lqfp thermal characteristics 1 symbol c parameter conditions 2 pin count value unit min typ max r ? ja cc d thermal resistance, junction-to-ambient natural convection 3 single-layer board ? 1s 100 ? ? 64 c/w 144 ? ? 64 176 ? ? 64 four-layer board ? 2s2p 100 ? ? 49.7 144 ? ? 48.3 176 ? ? 47.3 r ? jb cc thermal resistance, junction-to-board 4 single-layer board ? 1s 100 ? ? 36 c/w 144 ? ? 38 176 ? ? 38 four-layer board ? 2s2p 100 ? ? 33.6 144 ? ? 33.4 176 ? ? 33.4 MPC5606BK microcontroller data sheet, rev. 3 32 freescale semiconductor 3.5.3 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using equation 1 : t j = t a + (p d x r ? ja ) eqn. 1 where: t a is the ambient temperature in c. r ? ja is the package junction-to-ambie nt thermal resistance, in c/w. p d is the sum of p int and p i/o (p d = p int + p i/o ). p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications, p i/o < p int and may be neglected. on the other hand, p i/o may be significant, if the device is configured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273 c) eqn. 2 therefore, solving equations 1 and 2 : k = p d x (t a + 273 c) + r ? ja x p d 2 eqn. 3 where: r ? jc cc thermal resistance, junction-to-case 5 single-layer board ? 1s 100 ? ? 23 c/w 144 ? ? 23 176 ? ? 23 four-layer board ? 2s2p 100 ? ? 19.8 144 ? ? 19.2 176 ? ? 18.8 1 thermal characteristics are targets based on simulation. 2 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c. 3 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. when greek letters are not available, the symbols are typed as r thja and r thjma . 4 junction-to-board thermal resistance determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. when greek le tters are not available, the symbols are typed as r thjb . 5 junction-to-case at the top of the package determin ed using mil-std 883 meth od 1012.1. the cold plate temperature is used for the case temperature. reported value includes the thermal resistance of the interface layer. when greek letters are not available, the symbols are typed as r thjc . table 11. lqfp thermal characteristics 1 (continued) symbol c parameter conditions 2 pin count value unit min typ max MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 33 k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations 1 and 2 iteratively for any value of t a . 3.6 i/o pad electrical characteristics 3.6.1 i/o pad types the device provides four main i/o pad types depe nding on the associated alternate functions: ? slow pads ? are the most common pads, providing a good compromise between transition time and low electromagnetic emission. ? medium pads ? provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. ? fast pads ? provide maximum speed. these are used for improved debugging capability. ? input only pads ? are associated with adc channels and 32 khz low power external crystal oscillator providing low input leakage. medium and fast pads can use slow configuration to reduce elect romagnetic emission, at the cost of reducing ac performance. 3.6.2 i/o input dc characteristics table 12 provides input dc electrical ch aracteristics as described in figure 5 . figure 5. i/o input dc electrical characteristics definition v il v in v ih pdix = ?1 v dd v hys (gpdi register of siul) pdix = ?0? MPC5606BK microcontroller data sheet, rev. 3 34 freescale semiconductor 3.6.3 i/o output dc characteristics the following tables provide dc char acteristics for bidirectional pads: ? table 13 provides weak pull figures. both pull- up and pull-down resistances are supported. ? table 14 provides output driver char acteristics for i/o pads wh en in slow configuration. ? table 15 provides output driver char acteristics for i/o pads when in medium configuration. ? table 16 provides output driver char acteristics for i/o pads wh en in fast configuration. table 12. i/o input dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v ih sr p input high level cmos (schmitt trigger) ? 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ?? i lkg cc p digital input leakage no injection on adjacent pin t a = ? 40 c ? 2 ? na pt a = 25 c ? 2 ? dt a = 85 c ? 5 300 dt a = 105 c ? 12 500 pt a = 125 c ? 70 1000 w fi 2 2 in the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. sr p wakeup input filtered pulse ? ? ? 40 ns w nfi 2 sr p wakeup input not filtered pulse ? 1000 ? ? ns table 13. i/o pull-up/pull-down dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max |i wpu | cc p weak pull-up current absolute value v in = v il , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset are configured in input or in hi gh impedance state. 10 ? 250 pv in = v il , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 |i wpd | cc p weak pull-down current absolute value v in = v ih , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 10 ? 250 pv in = v ih , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 35 table 14. slow configuration output buffer electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v oh cc p output high level slow configuration push pull i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ??v ci oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configurat ion during power-up. all pads but reset are configured in inpu t or in high impedance state. 0.8v dd ?? ci oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? v ol cc p output low level slow configuration push pull i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v ci ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd ci ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 table 15. medium configuration output buffer electrical characteristics symbol c parameter conditions 1 value unit min typ max v oh cc c output high level medium configuration push pull i oh = ? 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v pi oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? ci oh = ? 1ma, v dd = 5.0 v 10%, pad3v5v = 1 2 0.8v dd ?? ci oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? ci oh = ? 100 a, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? MPC5606BK microcontroller data sheet, rev. 3 36 freescale semiconductor v ol cc c output low level medium configuration push pull i ol = 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.2v dd v pi ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd ci ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd ci ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 ci ol = 100 a, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.1v dd 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configurat ion during power-up. all pads but reset are configured in inpu t or in high impedance state. table 16. fast configuration output buffer electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v oh cc p output high level fast configuration push pull i oh = ? 14 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ??v ci oh = ? 7ma, v dd = 5.0 v 10%, pad3v5v = 1 2 0.8v dd ?? ci oh = ? 11 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? v ol cc p output low level fast configuration push pull i ol = 14 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v ci ol = 7 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd ci ol = 11 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 table 15. medium configuration output buff er electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 37 3.6.4 output pin transition times 3.6.5 i/o pad current specification the i/o pads are distributed across the i/o supply segm ent. each i/o supply segm ent is associated to a v dd /v ss supply pair as described in table 18 . table 19 provides i/o consumption figures. in order to ensure device reliability, the average current of the i/o on a si ngle segment should remain below the i av g s e g maximum value. 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset are configured in input or in high impedance state. table 17. output pin transition times symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max t tr cc d output transition time output pin 2 slow configuration 2 c l includes device and package capacitances (c pkg < 5 pf). c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ? ? 50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ??50 tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 t tr cc d output transition time output pin 2 medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ? ? 10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 t tr cc d output transition time output pin 2 fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ?? 4 ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 MPC5606BK microcontroller data sheet, rev. 3 38 freescale semiconductor table 18. i/o supply segments package supply segment 12345678 176 lqfp pin7 ? pin27 pin28 ? pin57 pin59 ? pin85 pin86 ? pin123 pin124 ? pin150 pin151 ? pin6 ? ? 144 lqfp pin20 ? pin49 pin51 ? pin99 pin100 ? pin122 pin 123 ? pin19 ? ? ? ? 100 lqfp pin16 ? pin35 pin37 ? pin69 pin70 ? pin83 pin84 ? pin15 ? ? ? ? table 19. i/o consumption symbol c parameter conditions 1 value unit min typ max i swtslw ,2 cc d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??20ma v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed 2 cc d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??29ma v dd = 3.3 v 10%, pad3v5v = 1 ??17 i swtfst 2 cc d dynamic i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??110ma v dd = 3.3 v 10%, pad3v5v = 1 ??50 i rmsslw cc d root medium square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 i rmsmed cc d root medium square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11 MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 39 table 20 provides the weight of concurrent switching i/os. in order to ensure device functionality, the sum of the weight of concurrent switching i/os on a single segment should remain below the 100%. i rmsfst cc d root medium square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??22ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 56 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 35 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to125 c, unless otherwise specified 2 stated maximum values represent peak consumption that lasts only a few ns during i/o transition. table 20. i/o weight 1 supply segment pad 176 lqfp 144/100 lqfp weight 5 v weight 3.3 v weight 5 v weight 3.3 v 176 lqfp 144 lqfp 100 lqfp src 2 =0 src=1 src=0 src=1 src=0 src=1 src=0 src=1 6 4 4 pb[3] 5% ? 6% ? 13% ? 15% ? pc[9] 4% ? 5% ? 13% ? 15% ? pc[14] 4% ? 4% ? 13% ? 15% ? pc[15] 3% 4% 4% 4% 12% 18% 15% 16% ? ? pj[4] 3% 4% 3% 3% ? ? ? ? table 19. i/o consumption (continued) symbol c parameter conditions 1 value unit min typ max MPC5606BK microcontroller data sheet, rev. 3 40 freescale semiconductor 1 ? ?ph[15]2% 3%3%3% ? ? ? ? ? ?ph[13]3% 4%3%4% ? ? ? ? ? ?ph[14]3% 4%4%4% ? ? ? ? ? ? pi[6] 4% ? 4% ? ? ? ? ? ? ? pi[7] 4% ? 4% ? ? ? ? ? 4 ? pg[5] 4% ? 5% ? 10% ? 12% ? ? pg[4] 4% 6% 5% 5% 9% 13% 11% 12% ? pg[3] 4% ? 5% ? 9% ? 11% ? ? pg[2] 4% 6% 5% 5% 9% 12% 10% 11% 4 pa[2] 4% ? 5% ? 8% ? 10% ? pe[0] 4% ? 5% ? 8% ? 9% ? pa[1] 4% ? 5% ? 8% ? 9% ? pe[1] 4% 6% 5% 6% 7% 10% 9% 9% pe[8] 4% 6% 5% 6% 7% 10% 8% 9% pe[9] 4% ? 5% ? 6% ? 8% ? pe[10] 4% ? 5% ? 6% ? 7% ? pa[0]4% 6%5%5%6%8%7%7% pe[11] 4% ? 5% ? 5% ? 6% ? table 20. i/o weight 1 (continued) supply segment pad 176 lqfp 144/100 lqfp weight 5 v weight 3.3 v weight 5 v weight 3.3 v 176 lqfp 144 lqfp 100 lqfp src 2 =0 src=1 src=0 src=1 src=0 src=1 src=0 src=1 MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 41 21 ? pg[9] 9% ? 10% ? 9% ? 10% ? ? pg[8] 9% ? 11% ? 9% ? 11% ? 1 pc[11] 9% ? 11% ? 9% ? 11% ? pc[10] 9% 13% 11% 12% 9% 13% 11% 12% ? pg[7] 9% ? 11% ? 9% ? 11% ? ? pg[6] 10% 14% 11% 12% 10% 14% 11% 12% 1 pb[0] 10% 14% 12% 12% 10% 14% 12% 12% pb[1] 10% ? 12% ? 10% ? 12% ? ? pf[9] 10% ? 12% ? 10% ? 12% ? ? pf[8] 10% 14% 12% 13% 10% 14% 12% 13% ? pf[12] 10% 15% 12% 13% 10% 15% 12% 13% 1 pc[6] 10% ? 12% ? 10% ? 12% ? pc[7] 10% ? 12% ? 10% ? 12% ? ? pf[10] 10% 14% 11% 12% 10% 14% 11% 12% ? pf[11] 9% ? 11% ? 9% ? 11% ? 1 pa[15] 8% 12% 10% 10% 8% 12% 10% 10% ? pf[13] 8% ? 10% ? 8% ? 10% ? 1 pa[14] 8% 11% 9% 10% 8% 11% 9% 10% pa[4] 7% ? 9% ? 7% ? 9% ? pa[13] 7% 10% 8% 9% 7% 10% 8% 9% pa[12] 7% ? 8% ? 7% ? 8% ? table 20. i/o weight 1 (continued) supply segment pad 176 lqfp 144/100 lqfp weight 5 v weight 3.3 v weight 5 v weight 3.3 v 176 lqfp 144 lqfp 100 lqfp src 2 =0 src=1 src=0 src=1 src=0 src=1 src=0 src=1 MPC5606BK microcontroller data sheet, rev. 3 42 freescale semiconductor 3 2 2 pb[9] 1% ? 1% ? 1% ? 1% ? pb[8] 1% ? 1% ? 1% ? 1% ? pb[10] 5% ? 6% ? 6% ? 7% ? ? pf[0] 5% ? 6% ? 6% ? 8% ? ? pf[1] 5% ? 6% ? 7% ? 8% ? ? pf[2] 6% ? 7% ? 7% ? 9% ? ? pf[3] 6% ? 7% ? 8% ? 9% ? ? pf[4] 6% ? 7% ? 8% ? 10% ? ? pf[5] 6% ? 7% ? 9% ? 10% ? ? pf[6] 6% ? 7% ? 9% ? 11% ? ? pf[7] 6% ? 7% ? 9% ? 11% ? ? ?pj[3]6%?7%????? ? ?pj[2]6%?7%????? ? ?pj[1]6%?7%????? ? ?pj[0]6%?7%????? ? ? pi[15] 6% ? 7% ? ? ? ? ? ? ? pi[14] 6% ? 7% ? ? ? ? ? 2 2 pd[0] 1% ? 1% ? 1% ? 1% ? pd[1] 1% ? 1% ? 1% ? 1% ? pd[2] 1% ? 1% ? 1% ? 1% ? pd[3] 1% ? 1% ? 1% ? 1% ? pd[4] 1% ? 1% ? 1% ? 1% ? pd[5] 1% ? 1% ? 1% ? 1% ? pd[6] 1% ? 1% ? 1% ? 2% ? pd[7] 1% ? 1% ? 1% ? 2% ? table 20. i/o weight 1 (continued) supply segment pad 176 lqfp 144/100 lqfp weight 5 v weight 3.3 v weight 5 v weight 3.3 v 176 lqfp 144 lqfp 100 lqfp src 2 =0 src=1 src=0 src=1 src=0 src=1 src=0 src=1 MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 43 4 2 2 pd[8] 1% ? 1% ? 1% ? 2% ? pb[4] 1% ? 1% ? 1% ? 2% ? pb[5] 1% ? 1% ? 1% ? 2% ? pb[6] 1% ? 1% ? 1% ? 2% ? pb[7] 1% ? 1% ? 1% ? 2% ? pd[9] 1% ? 1% ? 1% ? 2% ? pd[10] 1% ? 1% ? 1% ? 2% ? pd[11] 1% ? 1% ? 1% ? 2% ? 4 ? ? pb[11] 1% ? 1% ? ? ? ? ? ? ? pd[12] 11% ? 13% ? ? ? ? ? 2 2 pb[12] 11% ? 13% ? 15% ? 17% ? pd[13] 11% ? 13% ? 14% ? 17% ? pb[13] 11% ? 13% ? 14% ? 17% ? pd[14] 11% ? 13% ? 14% ? 17% ? pb[14] 11% ? 13% ? 14% ? 16% ? pd[15] 11% ? 13% ? 13% ? 16% ? pb[15] 11% ? 13% ? 13% ? 15% ? ? ? pi[8] 10% ? 12% ? ? ? ? ? ? ? pi[9] 10% ? 12% ? ? ? ? ? ? ? pi[10] 10% ? 12% ? ? ? ? ? ? ? pi[11] 10% ? 12% ? ? ? ? ? ? ? pi[12] 10% ? 12% ? ? ? ? ? ? ? pi[13] 10% ? 11% ? ? ? ? ? 2 2 pa[3] 9% ? 11% ? 11% ? 13% ? ? pg[13] 9% 13% 11% 11% 10% 14% 12% 13% ? pg[12] 9% 13% 10% 11% 10% 14% 12% 12% ? ph[0] 6% 8% 7% 7% 6% 9% 7% 8% ? ph[1] 6% 8% 7% 7% 6% 8% 7% 7% ? ph[2] 5% 7% 6% 6% 5% 7% 6% 7% ? ph[3] 5% 7% 5% 6% 5% 7% 6% 6% ? pg[1] 4% ? 5% ? 4% ? 5% ? ? pg[0] 4% 5% 4% 5% 4% 5% 4% 5% table 20. i/o weight 1 (continued) supply segment pad 176 lqfp 144/100 lqfp weight 5 v weight 3.3 v weight 5 v weight 3.3 v 176 lqfp 144 lqfp 100 lqfp src 2 =0 src=1 src=0 src=1 src=0 src=1 src=0 src=1 MPC5606BK microcontroller data sheet, rev. 3 44 freescale semiconductor 53 ? pf[15] 4% ? 4% ? 4% ? 4% ? ? pf[14] 4% 6% 5% 5% 4% 6% 5% 5% ? pe[13] 4% ? 5% ? 4% ? 5% ? 3 pa[7] 5% ? 6% ? 5% ? 6% ? pa[8] 5% ? 6% ? 5% ? 6% ? pa[9] 6% ? 7% ? 6% ? 7% ? pa[10] 6% ? 8% ? 6% ? 8% ? pa[11] 8% ? 9% ? 8% ? 9% ? pe[12] 8% ? 9% ? 8% ? 9% ? ? pg[14] 8% ? 9% ? 8% ? 9% ? ? pg[15] 8% 11% 9% 10% 8% 11% 9% 10% ? pe[14] 8% ? 9% ? 8% ? 9% ? ? pe[15] 8% 11% 9% 10% 8% 11% 9% 10% ? pg[10] 8% ? 9% ? 8% ? 9% ? ? pg[11] 7% 11% 9% 9% 7% 11% 9% 9% ? ? ph[11] 7% 10% 9% 9% ? ? ? ? ? ? ph[12] 7% 10% 8% 9% ? ? ? ? ? ? pi[5] 7% ? 8% ? ? ? ? ? ? ? pi[4] 7% ? 8% ? ? ? ? ? 3 3 pc[3] 6% ? 8% ? 6% ? 8% ? pc[2]6% 8%7%7%6%8%7%7% pa[5]6% 8%7%7%6%8%7%7% pa[6] 5% ? 6% ? 5% ? 6% ? ph[10] 5% 7% 6% 6% 5% 7% 6% 6% pc[1] 5% 19% 5% 13% 5% 19% 5% 13% table 20. i/o weight 1 (continued) supply segment pad 176 lqfp 144/100 lqfp weight 5 v weight 3.3 v weight 5 v weight 3.3 v 176 lqfp 144 lqfp 100 lqfp src 2 =0 src=1 src=0 src=1 src=0 src=1 src=0 src=1 MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 45 3.7 reset electrical characteristics the device implements a dedi cated bidirectional reset pin. 6 4 4 pc[0] 6% 9% 7% 8% 7% 10% 8% 8% ph[9] 7% ? 8% ? 7% ? 9% ? pe[2] 7% 10% 8% 9% 8% 11% 9% 10% pe[3] 7% 10% 9% 9% 8% 12% 10% 10% pc[5] 7% 11% 9% 9% 8% 12% 10% 11% pc[4] 8% 11% 9% 10% 9% 13% 10% 11% pe[4] 8% 11% 9% 10% 9% 13% 11% 12% pe[5] 8% 11% 10% 10% 9% 14% 11% 12% ? ph[4] 8% 12% 10% 10% 10% 14% 12% 12% ? ph[5] 8% ? 10% ? 10% ? 12% ? ? ph[6] 8% 12% 10% 11% 10% 15% 12% 13% ? ph[7] 9% 12% 10% 11% 11% 15% 13% 13% ? ph[8] 9% 12% 10% 11% 11% 16% 13% 14% 4 pe[6] 9% 12% 10% 11% 11% 16% 13% 14% pe[7] 9% 12% 10% 11% 11% 16% 14% 14% ? ? pi[3] 9% ? 10% ? ? ? ? ? ? ? pi[2] 9% ? 10% ? ? ? ? ? ? ? pi[1] 9% ? 10% ? ? ? ? ? ? ? pi[0] 9% ? 10% ? ? ? ? ? 4 4 pc[12] 8% 12% 10% 11% 12% 18% 15% 16% pc[13] 8% ? 10% ? 13% ? 15% ? pc[8] 8% ? 10% ? 13% ? 15% ? pb[2] 8% 11% 9% 10% 13% 18% 15% 16% 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 src is the slew rate control bit in siu_pcr x table 20. i/o weight 1 (continued) supply segment pad 176 lqfp 144/100 lqfp weight 5 v weight 3.3 v weight 5 v weight 3.3 v 176 lqfp 144 lqfp 100 lqfp src 2 =0 src=1 src=0 src=1 src=0 src=1 src=0 src=1 MPC5606BK microcontroller data sheet, rev. 3 46 freescale semiconductor figure 6. start-up reset requirements figure 7. noise filtering on reset signal table 21. reset electrical characteristics symbol c parameter conditions 1 value unit min typ max v ih sr p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 47 v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ?? v v ol cc p output low level push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 2 ? ? 0.1v dd push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc d output transition time output pin 3 medium configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 10 ns c l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 20 c l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 40 c l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 12 c l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 25 c l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 40 w frst sr p reset input filtered pulse ? ? ? 40 ns w nfrst sr p reset input not filtered pulse ? 1000 ? ? ns |i wpu | cc p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 v dd = 5.0 v 10%, pad3v5v = 1 4 10 ? 250 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 this is a transient configuration during power-up, up to the end of reset phase2 (refer to the mc_rgm chapter of the MPC5606BK microcontroller reference manual ). 3 c l includes device and package capacitance (c pkg <5pf). 4 the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration during power-up. all pads but reset are configured in input or in high impedance state. table 21. reset electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max MPC5606BK microcontroller data sheet, rev. 3 48 freescale semiconductor 3.8 power management electrical characteristics 3.8.1 voltage regulator electrical characteristics the device implements an internal voltage regulator to generate the low voltage core supply v dd_lv from the high voltage ballast supply v dd_bv . the regulator itself is supplied by the common i/o supply v dd . the following supplies are involved: ? hv: high voltage external power supply for voltage regulator module. this must be provided externally through v dd power pin. ? bv: high voltage external power supply for internal ballast module. this must be provided externally through v dd_bv power pin. voltage values should be aligned with v dd . ? lv: low voltage internal power supply for core, fmpll and flash digital logic. this is generated by the internal voltage regulator but provided outside to connect stability capacito r. it is further split into four main domains to ensure noise isolation between critical lv modules within the device: ? lv_cor: low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ? lv_cfla: low voltage supply for code flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_dfla: low voltage supply for data flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_pll: low voltage supply for fmpll. it is shorted to lv_cor through double bonding. figure 8. voltage regulator capacitance connection the internal voltage regulator requires external capacitance (c regn ) to be connected to the device in order to provide a stable low voltage digital supply to the device. ca pacitances should be placed on the board as near as po ssible to the associated pins . care should also be taken to limit the seri al inductance of the board to less than 5 nh. c reg1 (lv_cor/lv_dfla) device v ss_lv v dd_bv v dd_lv c dec1 (ballast decoupling) v ss_lv v dd_lv v dd v ss_lv v dd_lv c reg2 (lv_cor/lv_cfla) c reg3 (lv_cor/lv_pll) c dec2 (supply/io decoupling) device v dd_bv i v dd_lvn v ref v dd voltage regulator v ss v ss_lvn gnd gnd gnd gnd MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 49 each decoupling capacitor must be placed between each of the three v dd_lv /v ss_lv supply pairs to ensure stable voltage (see section 3.4, recommended operating conditions ). the internal voltage regulator requires controlled slew rate of v dd /v dd_bv as described in figure 9 . figure 9. v dd and v dd_bv maximum slope when standby mode is used, further constraints apply to the v dd /v dd_bv in order to guarantee correct regulator functionality during standby exit. this is described in figure 10 . standby regulator constraints should normally be guaranteed by implementing equivalent of c stdby capacitance on application board (capacitance and esr typical values), but would actually depend on the ex act characteristics of the application?s external regulator. v dd_hv power up power down v dd_hv (max) functional range v dd_hv (min) MPC5606BK microcontroller data sheet, rev. 3 50 freescale semiconductor figure 10. v dd and v dd_bv supply constraints during standby mode exit table 22. voltage regulator electrical characteristics symbol c parameter conditions 1 value unit min typ max c regn sr ? internal voltage regulator external capacitance ? 200 ? 500 nf r reg sr ? stability capacitor equivalent serial resistance ???0.2 ? c dec1 sr ? decoupling capacitance 2 ballast v dd_bv /v ss_lv pair: v dd_bv = 4.5 v to 5.5 v 100 3 470 4 ?nf v dd_bv /v ss_lv pair: v dd_bv = 3v to 3.6v 400 ? c dec2 sr ? decoupling capacitance regulator supply v dd /v ss pair 10 100 ? nf v mreg cc p main regulator output voltage before exiting from reset ? 1.32 ? v after trimming 1.15 1.28 1.32 i mreg sr ? main regulator current provided to v dd_lv domain ??? 150 ma v dd_hv v dd_hv (min) vdd(stdby) v dd_hv v dd_hv (max) v dd_lv t d d vdd stdby () t d d vdd stdby () vdd(stdby) v dd_lv (nominal) 0v MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 51 3.8.2 voltage monitor electrical characteristics the device implements a power-on reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the v dd and the v dd_lv voltage while device is supplied: i mregint cc d main regulator module current consumption i mreg = 200 ma ? ? 2 ma i mreg = 0 ma ? ? 1 v lpreg cc p low power regulator output voltage after trimming 1.15 1.23 1.32 v i lpreg sr ? low power regulator current provided to v dd_lv domain ??? 15 ma i lpregint cc d low power regulator module current consumption i lpreg = 15 ma; t a = 55 c ?? 600 a ? i lpreg = 0 ma; t a = 55 c ? 5? v ulpreg cc p ultra low power regulator output voltage after trimming 1.15 1.23 1.32 v i ulpreg sr ? ultra low power regulator current provided to v dd_lv domain ??? 5 ma i ulpregint cc d ultra low power regulator module current consumption i ulpreg = 5 ma; t a = 55 c ?? 100 a i ulpreg = 0 ma; t a = 55 c ? 2? i dd_bv cc d inrush average current on v dd_bv during power-up 5 ?? ? 300 6 ma sr ? maximum slope on vdd ? ?? 250 mv/s sr ? maximum instant variation on vdd during standby exit ? ?? 30 mv sr ? maximum slope on vdd during standby exit ? ?? 15 mv/s 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 this capacitance value is driven by the constraint s of the external voltage regulator supplying the v dd_bv voltage. a typical value is in the range of 470 nf. 3 this value is acceptable to guar antee operation from 4.5 v to 5.5 v 4 external regulator and capacitance circ uitry must be capable of providing i dd_bv while maintaining supply v dd_bv in operating range. 5 inrush current is seen only for short time during power-up an d on standby exit (max 20 s, depending on external capacitances to be load). 6 the duration of the inrush current d epends on the capacitance placed on lv pi ns. bv decoupling capacitors must be sized accordingly. refer to i mreg value for minimum amount of current to be provided in cc. table 22. voltage regulator electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max t d d vdd ? vdd stdby ? ?? t d d vdd stdby ?? MPC5606BK microcontroller data sheet, rev. 3 52 freescale semiconductor ? por monitors v dd during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply ? lvdhv3b monitors v dd_bv to ensure device reset below minimum functional supply ? lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range ? lvdlvcor monitors power domain no. 1 ? lvdlvbkp monitors power domain no. 0 note when enabled, power domain no. 2 is monitored through lvdlvbkp. figure 11. low voltage monitor vs. reset table 23. low voltage monitor electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v porup sr d supply for functional por module t a = 25 c, after trimming 1.0 ? 5.5 v v porh cc p power-on reset threshold 1.5 ? 2.6 v lv d h v 3 h cc t lvdhv3 low voltage detector high threshold ? ? 2.95 v lv d h v 3 l cc p lvdhv3 low voltage detector low threshold 2.6 ? 2.9 v lvdhv3bh cc t lvdhv3b low voltage detector high threshold ? ? 2.95 v lvdhv3bl cc p lvdhv3bl low voltage detector low threshold 2.6 ? 2.9 v lv d h v 5 h cc t lvdhv5 low voltage detector high threshold ? ? 4.5 v lv d h v 5 l cc p lvdhv5 low voltage detector low threshold 3.8 ? 4.4 v lv d lvc o r l cc p lvdlvcor low voltage detector low threshold 1.08 ? ? v lvdlvbkpl cc p lvdlvbkp low voltage detec tor low threshold 1.08 ? 1.14 v dd v lvdhvxh reset v lvdhvxl MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 53 3.9 power consumption in different application modes table 24 provides dc electrical characteristic s for significant application modes. th ese values are indi cative values; actual consumption depends on the application. table 24. electrical characteristics in different application modes 1 1 except for i ddmax , all consumptions in this table apply to v dd_bv only and do not include v dd_hv . symbol c parameter conditions 2 2 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max i ddmax 3 3 running consumption is given on voltage regulator supply (v ddreg ). i ddmax is composed of three components: i ddmax = i dd (v dd_bv ) + i dd (v dd_hv ) + i dd (v dd_hv_adc ). it does not include a fourth component linked to i/os toggling which is highly dependent on the application. the given value is thought to be a worst case value (64 mhz at 125 c) with all peripherals running, and code fetched from code flash while modify operation on-going on data flash. note that this value can be significantl y reduced by the application: switch off unused peripherals (default), reduce peripheral frequency through internal pr escaler, fetch from ram most used functions, use low power mode when possible. cc c run mode maximum average current ? ? 81 130 4 ma i ddrun 5 cc t run mode typical average current 6 f cpu = 8 mhz ? 12 ? ma tf cpu = 16 mhz ? 27 ? cf cpu = 32 mhz ? 40 ? pf cpu = 48 mhz ? 54 95 pf cpu = 64 mhz ? 67 120 i ddhalt cc c halt mode current 7 slow internal rc oscillator (128 khz) running t a = 25 c ? 10 15 ma pt a = 125 c ? 15 28 i ddstop cc p stop mode current 8 slow internal rc oscillator (128 khz) running t a = 25 c ? 130 500 a dt a =55c ? 180 ? dt a =85c ? 1 5 ma dt a = 105 c ? 3 9 pt a = 125 c ? 5 14 i ddstdby2 cc p standby2 mode current 9 slow internal rc oscillator (128 khz) running t a = 25 c ? 17 80 a ct a =55c ? 30 ? ct a =85c ? 110 ? ct a = 105 c ? 280 950 ct a = 125 c ? 460 1700 i ddstdby1 cc c standby1 mode current 10 slow internal rc oscillator (128 khz) running t a = 25 c ? 12 50 a ct a =55c ? 24 ? ct a =85c ? 48 ? ct a = 105 c ? 150 500 ct a = 125 c ? 260 ? MPC5606BK microcontroller data sheet, rev. 3 54 freescale semiconductor 3.10 flash memory electrical characteristics 3.10.1 program/erase characteristics table 25 shows the program and erase characteristics. 4 higher current may be sunk by device during power-up and standby exit. please refer to inrush current in ta b l e 2 2 . 5 run current measured with typical applicatio n with accesses on both flash and ram. 6 only for the ?p? classification: data and code flash in normal power. code fetched from ram: serial ips can and lin in loop back mode, dspi as master, pll as system clock (4 x multiplier) peripherals on (e mios/ctu/adc) and running at max frequency, periodic sw/wdg timer reset enabled. 7 data flash power down. code flash in low power. sirc 128 khz and firc 16 mhz on. 10 mhz xtal clock. flexcan: instances: 0, 1, 2 on (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. linflex: instances: 0, 1, 2 on (clocked but not reception or trans mission), instance: 3 to 9 cl ocks gated. emios: instance: 0 on (16 channels on pa[0]?pa[11] and pc[12]?pc[15 ]) with pwm 20 khz, instance: 1 clock gated. dspi: instance: 0 (clocked but no communication), instance: 1 to 5 clocks gated. rtc/api on. pit on. stm on. adc1 off. adc0 on but no conversion except two analog watchdogs. 8 only for the ?p? classification: no clock, firc 16 mhz off, sirc 128 khz on, pll off, hpvreg off, ulpvreg/lpvreg on. all possible peripherals off and clock gated. flash in power down mode. 9 only for the ?p? classification: ulpreg on, hp/lpvreg off, 32 kb ram on, device configured for minimum consumption, all possible modules switched off. 10 ulpreg on, hp/lpvreg off, 8 kb ram on, device confi gured for minimum consumption, all possible modules switched off. table 25. program and erase specifications symbol c parameter conditions value unit min typ 1 initial max 2 max 3 t dwprogram cc c double word (64 bits) program time 4 code flash ? 18 50 500 s data flash 22 t 16kpperase 16 kb block preprogram and erase time code flash ? 200 500 5000 ms data flash 300 t 32kpperase 32 kb block preprogram and erase time code flash ? 300 600 5000 ms data flash 400 t 32kpperase 32 kb block preprogram and erase time for sector b0f4 code flash ? 600 1200 10000 ms t 128kpperase 128 kb block preprogram and erase time code flash ? 600 1300 7500 ms data flash 800 t 128kpperase 128 kb block preprogram and erase time for sector b0f5 code flash ? 1200 2600 15000 ms t eslat d erase suspend latency ? ? ? 30 30 s t esrt c erase suspend request rate code flash 20 ? ? ? ms data flash 10 ? ? ? MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 55 ecc circuitry provides correction of single bit faults and is us ed to improve further automotive reliability results. some unit s will experience single bit corrections throughout the life of the product with no impact to product reliability. 3.10.2 flash power supply dc characteristics table 28 shows the power supply dc char acteristics on external supply. 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. 2 initial factory condition: < 100 program/er ase cycles, 25 c, typical supply voltage. 3 the maximum program and erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. 4 actual hardware programming times. this does not include software overhead. table 26. flash module life symbol c parameter conditions value unit min typ max p/e cc c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100000 ? ? cycles p/e cc c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ? 10000 100000 ? cycles p/e cc c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ? 1000 100000 ? cycles retention cc c minimum data retention at 85 c average ambient temperature 1 1 ambient temperature averaged over duration of applic ation, not to exceed recommended product operating temperature range. blocks with 0?1,000 p/e cycles 20 ? ? years blocks with 1,001?10,000 p/e cycles 10 ? ? years blocks with 10,001?100,000 p/e cycles 5??years table 27. flash read access timing symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. max unit f read cc p maximum frequency for flash reading 2 wait states 64 mhz c 1 wait state 40 c 0 wait states 20 MPC5606BK microcontroller data sheet, rev. 3 56 freescale semiconductor 3.10.3 start-up/switch-off timings 3.11 electromagnetic compatib ility (emc) characteristics susceptibility tests are performed on a sa mple basis during produ ct characterization. 3.11.1 designing hardened software to avoid noise problems emc characterization and optimiza tion are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. table 28. flash power supply dc electrical characteristics symbol parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified. value unit min typ max i cfread cc sum of the current consumption on v ddhv and v ddbv on read access flash module read f cpu = 64 mhz 2 2 f cpu 64 mhz can be achieved at up to 125 c. code flash ? ? 33 ma i dfread data flash ? ? 33 i cfmod cc sum of the current consumption on v ddhv and v ddbv on matrix modification (program/erase) program /erase on-going while reading flash registers f cpu = 64 mhz 2 code flash ? ? 52 ma i dfmod data flash ? ? 33 i cflpw cc sum of the current consumption on v ddhv and v ddbv during flash low power mode ? code flash ? ? 1.1 ma i dflpw data flash ? ? 900 a i cfpwd cc sum of the current consumption on v ddhv and v ddbv during flash power down mode ? code flash ? ? 150 a i dfpwd data flash ? ? 150 table 29. start-up time/switch-off time symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max t flarstexit cc t delay for flash module to exit reset mode ? ? ? 125 s t flalpexit cc t delay for flash module to exit low-power mode ? ? ? 0.5 t flapdexit cc t delay for flash module to exit power-down mode ???30 t flalpentry cc t delay for flash module to enter low-power mode ???0.5 t flapdentry cc t delay for flash module to enter power-down mode ???1.5 MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 57 therefore it is recommended that the user apply emc software optimization and prequalification tests in relation with the emc level requested for the application. ? software recommendations ?? the software flowchart must include the ma nagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) ? prequalification trials ?? most of the common failures (unexpected re set and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prev ent unrecoverable errors occurring. 3.11.2 electromagnetic interference (emi) the product is monitored in terms of emission based on a typical application. this emission test conforms to the iec61967-1 standard, which specifies the general conditions for emi measurements. 3.11.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement me thods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 3.11.3.1 electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) ar e applied to the pins of each sample accord ing to each pin combination. the sample size depends on the number of supply pins in the device (3 parts ? (n + 1) supply pin). this test conforms to the aec- q100-002/-003/-011 standard. table 30. emi radiated emission measurement 1,2 1 emi testing and i/o port waveforms per iec 61967-1, -2, -4 2 for information on conducted emission and susceptibility measurement (norm iec 61967-4), please contact your local marketing representative. symbol c parameter conditions value unit min typ max ? sr ? scan range ? 0.150 1000 mhz f cpu sr ? operating frequency ? ? 64 ? mhz v dd_lv sr ? lv operating voltages ? ? 1.28 ? v s emi cc t peak level v dd = 5v, t a =25c, lqfp144 package test conforming to iec 61967-2, f osc = 8 mhz/f cpu = 64 mhz no pll frequency modulation ? ? 18 dbv 2% pll frequency modulation ? ? 14 dbv MPC5606BK microcontroller data sheet, rev. 3 58 freescale semiconductor 3.11.3.2 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is appl ied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 3.12 fast external crystal oscill ator (4 to 16 mhz) electrical characteristics the device provides an oscillator/resonator driver. figure 12 describes a simple model of the internal oscillat or driver and provides an example of a connection for an oscillator or a resonator. table 33 provides the parameter description of 4 mhz to 16 mhz crystals used for the design simulations. table 31. esd absolute maximum ratings 1,2 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for au tomotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and f unctional testing shall be performed per applicable device specification at room temperature followed by ho t temperature, unless specified otherwise in the device specification. symbol ratings conditions class max value 3 3 data based on characterization results, not tested in production unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v esd(cdm) electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 750 (corners) table 32. latch-up results symbol parameter conditions class lu static latch-up class t a = 125 c conforming to jesd 78 ii level a MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 59 figure 12. crystal oscillator and resonator connection scheme note xtal/extal must not be directly used to drive external circuits. table 33. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr ? crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c1 = c2 (pf) 1 1 the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, et c.) as the ac / transient behavior depends upon them. shunt capacitance between xtalout and xtalin c0 2 (pf) 2 the value of c0 specified here includes 2 pf additional capacitance for parasitics (to be seen with bond-pads, package, etc.). 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 c2 c1 crystal xtal extal resonator xtal extal device device device xtal extal i r v dd MPC5606BK microcontroller data sheet, rev. 3 60 freescale semiconductor figure 13. fast external crystal oscillator (4 to 16 mhz) electrical characteristics table 34. fast external crystal oscillator (4 to 16 mhz) electrical characteristics symbol c parameter conditions 1 value unit min typ max f fxosc sr ? fast external crystal oscillator frequency ?4.0?16.0mhz g mfxosc cc c fast external crystal oscillator transconductance v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 0 2.2 ? 8.2 ma/v cc p v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 0 2.0 ? 7.4 cc c v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 1 2.7 ? 9.7 cc c v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 1 2.5 ? 9.2 v fxosc cc t oscillation amplitude at extal f osc =4mhz, oscillator_margin = 0 1.3 ? ? v f osc =16mhz, oscillator_margin = 1 1.3 ? ? v fxoscop cc p oscillation operating point ? ? 0.95 v i fxosc 2 cc t fast external crystal oscillator consumption ??23ma v mxoscop t mxoscsu v xtal v mxosc valid internal clock 90% 10% 1/f mxosc s_mtrans bit (me_gs register) 1 0 MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 61 3.13 slow external crystal oscillator (32 khz) electrical characteristics the device provides a low power oscillator/resonator driver. figure 14. crystal oscillator and resonator connection scheme note osc32k_xtal/osc32k_extal must not be dir ectly used to drive external circuits. t fxoscsu cc t fast external crystal oscillator start-up time f osc = 4 mhz, oscillator_margin = 0 ?? 6ms f osc = 16 mhz, oscillator_margin = 1 ??1.8 v ih sr p input high level cmos (schmitt trigger) oscillator bypass mode 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) oscillator bypass mode ? 0.4 ? 0.35v dd v 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 stated values take into account only analog module cons umption but not the digital contributor (clock tree and enabled peripherals). table 34. fast external crystal oscillator (4 to 16 mhz) electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max osc32k_xtal osc32k_extal device c2 c1 crystal osc32k_xtal osc32k_extal r p resonator device MPC5606BK microcontroller data sheet, rev. 3 62 freescale semiconductor l figure 15. equivalent circuit of a quartz crystal table 35. crystal motional characteristics 1 1 the crystal used is epson toyocom mc306. symbol parameter conditions value unit min typ max l m motional inductance ? ? 11.796 ? kh c m motional capacitance ? ? 2 ? ff c1/c2 load capacitance at osc32k_xtal and osc32k_extal with respect to ground 2 2 this is the recommended range of load capacitance at osc32k_xtal and osc32k_extal with respect to ground. it includes all the parasitics due to board traces, crystal and package. ?18?28pf r m 3 3 maximum esr (r m ) of the crystal is 50 k ? motional resistance ac coupled at c0 = 2.85 pf 4 4 c0 includes a parasitic capacitance of 2.0 pf between osc32k_xtal and osc32k_extal pins. ??65k ? ac coupled at c0 = 4.9 pf 4 ??50 ac coupled at c0 = 7.0 pf 4 ??35 ac coupled at c0 = 9.0 pf 4 ??30 c0 c2 c1 c2 r m c1 l m c m crystal MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 63 figure 16. slow external crystal oscillator (32 khz) electrical characteristics 3.14 fmpll electrical characteristics the device provides a frequency modulated phase locked loop (f mpll) module to generate a fast system clock from the fxosc or firc sources. table 36. slow external crystal oscillator (32 khz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max f sxosc sr ? slow external crystal oscillator frequency ? 32 32.768 40 khz v sxosc cc t oscillation amplitude ? ? 2.1 ? v i sxoscbias cc t oscillation bias current ? 2.5 a i sxosc cc t slow external crystal oscillator consumption ???8a t sxoscsu cc t slow external crystal oscillator start-up time ???2 2 2 start-up time has been measured with epson toyocom mc3 06 crystal. variation may be seen with other crystal. s table 37. fmpll electrical characteristics symbol c parameter conditions 1 value unit min typ max f pllin sr ? fmpll reference clock 2 ?4?64mhz ? pllin sr ? fmpll reference clock duty cycle 2 ?40?60% oscon bit (osc_ctl register) t lpxosc32ksu 1 v osc32k_xtal v lpxosc32k valid internal clock 90% 10% 1/f lpxosc32k 0 MPC5606BK microcontroller data sheet, rev. 3 64 freescale semiconductor 3.15 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a 16 mhz main internal rc oscillator. this is used as the default clock at the power-up of the device. f pllout cc p fmpll output clock frequency ? 16 ? 64 mhz f vco 3 cc p vco frequency without frequency modulation ? 256 ? 512 mhz p vco frequency with frequency modulation ? 245.76 ? 532.48 f cpu sr ? system clock frequency ? ? ? 64 4 mhz f free cc p free-running frequency ? 20 ? 150 mhz t lock cc p fmpll lock time stable oscillator (f pllin = 16 mhz) 40 100 s ? t stjit cc ? fmpll short term jitter 5 f sys maximum ?4 ? 4 % ? t ltjit cc ? fmpll long term jitter f pllclk at 64 mhz, 4000 cycles ? ? 10 ns i pll cc c fmpll consumption t a = 25 c ? ? 4 ma 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 pllin clock retrieved directly from fxosc clock. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and ? pllin . 3 frequency modulation is considered 4%. 4 f cpu 64 mhz can be achieved only at up to 125 c. 5 short term jitter is measured on the clock rising edge at cycle n and n +4. table 38. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions 1 value unit min typ max f firc cc p fast internal rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mhz sr ? ? 12 20 i fircrun 2, cc t fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? 200 a i fircpwd cc d fast internal rc oscillator high frequency current in power down mode t a = 25 c ? ? 10 a i fircstop cc t fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 500 ? a sysclk = 2 mhz ? 600 ? sysclk = 4 mhz ? 700 ? sysclk = 8 mhz ? 900 ? sysclk = 16 mhz ? 1250 ? table 37. fmpll electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 65 3.16 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz low power internal rc oscillator. this can be used as the reference clock for the rtc module. t fircsu cc c fast internal rc oscillator start-up time v dd = 5.0 v 10% ? 1.1 2.0 s ? fircpre cc c fast internal rc oscillator precision after software trimming of f firc t a = 25 c ? 1? 1% ? firctrim cc c fast internal rc oscillator trimming step t a = 25 c ? 1.6 % ? fircvar cc c fast internal rc oscillator variation over temperature and supply with respect to f firc at t a = 25 c in high-frequency configuration ? ? 5? 5% 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. table 39. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max f sirc cc p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz sr ? ? 100 ? 150 i sirc 2, 2 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. cc c slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu cc p slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% ? 8 12 s ? sircpre cc c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2? 2% ? sirctrim cc c slow internal rc oscillator trimming step ??2.7? ? sircvar cc c slow internal rc oscillator variation in temperature and supply with respect to f sirc at t a = 55 c in high frequency configuration high frequency configuration ? 10 ? 10 % table 38. fast internal rc oscillator (16 mhz) electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max MPC5606BK microcontroller data sheet, rev. 3 66 freescale semiconductor 3.17 adc electrical characteristics 3.17.1 introduction the device provides two successive appr oximation register (sar) analog-to-digital convert ers (10-bit and 12-bit). figure 17. adc_0 characteristic and error definitions 3.17.2 input impedance and adc accuracy in the following analysis, the input circuit corres ponding to the precise ch annels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dd_adc / 1024 MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 67 possible, ideally infinite. this capacitor contributes to attenuat ing the noise present on the input pin; furthermore, it sourc es charge during the sampling phase, when the anal og signal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (fc c s ), where fc represents the conversion rate at the consider ed channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 4 : eqn. 4 equation 4 generates a constraint for external network design, in pa rticular on resistive path. in ternal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 18. input equivalent circuit (precise channels) v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb ? r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a MPC5606BK microcontroller data sheet, rev. 3 68 freescale semiconductor figure 19. input equivalent circuit (extended channels) a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 18 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 20. transient behavior during sampling phase in particular two different transient periods can be distinguished: 1. a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 69 eqn. 5 equation 5 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : eqn. 7 2. a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: eqn. 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 9 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 10 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to ac t as antialiasing. ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ? ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ? ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = MPC5606BK microcontroller data sheet, rev. 3 70 freescale semiconductor figure 21. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a consequence the cut-off fr equency of the antialiasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant time of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed ch annel continuous conversion mode is select ed (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : eqn. 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v ), assuming to accept a maximum error of half a count, a constraint is evident on c f value: adc_0 (10-bit) eqn. 12 adc_1 (12-bit) eqn. 13 f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 < f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c < 2 r f c f (conversion rate vs. filter pole) noise v a2 v a ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ? c f 8192 c s ? ? MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 71 3.17.3 adc electrical characteristics table 40. adc input leakage current symbol c parameter conditions value unit min typ max i lkg cc c input leakage current t a = ? 40 c no current injection on adjacent pin ? 1 ? na ct a = 25 c ? 1 ? dt a = 85 c 3 100 ct a = 105 c ? 8 200 pt a = 125 c ? 45 400 table 41. adc_0 conversion characteristics (10-bit adc_0) symbol c parameter conditions 1 value unit min typ max v ss_adc0 sr ? voltage on vss_hv_adc0 (adc_0 reference) pin with respect to ground (v ss ) 2 ? ? 0.1 ? 0.1 v v dd_adc0 sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?v dd ? 0.1 ? v dd +0.1 v v ainx sr ? analog input voltage 3 ?v ss_adc0 ? 0.1 ?v dd_adc0 +0.1 v i adc0pwd sr ? adc_0 consumption in power down mode ???50a i adc0run sr ? adc_0 consumption in running mode ? ? ? 40 ma f adc0 sr ? adc_0 analog frequency ? 6? 32 + 4% mhz ? adc0_sys sr ? adc_0 digital clock duty cycle (ipg_clk) adclksel = 1 4 45 ? 55 % t adc0_pu sr ? adc_0 power up delay ? ?? 1.5 s t adc0_s cc t sample time 5 f adc = 32 mhz, adc0_conf_sample_input = 17 0.5 ? s f adc = 6 mhz, inpsamp = 255 ??42 t adc0_c cc p conversion time 6 f adc = 32 mhz, adc_conf_comp = 2 0.625 ? ? s c s cc d adc_0 input sampling capacitance ??? 3 pf c p1 cc d adc_0 input pin capacitance 1 ? ? ? 3 pf c p2 cc d adc_0 input pin capacitance 2 ??? 1 pf c p3 cc d adc_0 input pin capacitance 3 ? ? ? 1 pf MPC5606BK microcontroller data sheet, rev. 3 72 freescale semiconductor r sw1 cc d internal resistance of analog source ??? 3 k ? r sw2 cc d internal resistance of analog source ? ? ? 2 k ? r ad cc d internal resistance of analog source ??? 2 k ? i inj sr ? input current injection current injection on one adc_0 input, different from the converted one v dd = 3.3 v 10% ? 5? 5 ma v dd = 5.0 v 10% ? 5 ? 5 | inl | cc t absolute value for integral nonlinearity no overload ? 0.5 1.5 lsb | dnl | cc t absolute differential nonlinearity no overload ? 0.5 1.0 lsb | ofs | cc t absolute offset error ? ? 0.5 ? lsb | gne | cc t absolute gain error ?? 0.6 ? lsb tuep cc p total unadjusted error 7 for precise channels, input only pins without current injection ? 2 0.6 2 lsb t with current injection ? 3 ? 3 tuex cc t total unadjusted error 7 for extended channel without current injection ? 3 1 3 lsb t with current injection ? 4 4 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 analog and digital v ss must be common (to be tied together externally). 3 v ainx may exceed v ss_adc0 and v dd_adc0 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff. 4 duty cycle is ensured by using system clock without pr escaling. when adclksel = 0, the duty cycle is ensured by internal divider by 2. 5 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t adc0_s . after the end of the sample time t adc0_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc0_s depend on programming. 6 this parameter does not include the sample time t adc0_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. 7 total unadjusted error: the maximum erro r that occurs without adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 41. adc_0 conversion characteristics (10-bit adc_0) (continued) symbol c parameter conditions 1 value unit min typ max MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 73 figure 22. adc_1 characteristic and error definitions table 42. adc_1 conversion characteristics (12-bit adc_1) symbol c parameter conditions 1 value unit min typ max v ss_adc1 sr ? voltage on vss_hv_adc1 (adc_1 reference) pin with respect to ground (v ss ) 2 ??0.1?0.1v v dd_adc1 sr ? voltage on vdd_hv_adc1 pin (adc_1 reference) with respect to ground (v ss ) ?v dd ?0.1 ? v dd +0.1 v (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 1 lsb ideal = avdd / 4096 MPC5606BK microcontroller data sheet, rev. 3 74 freescale semiconductor v ainx sr ? analog input voltage 3 ?v ss_adc1 ?0.1 ?v dd_adc1 +0.1 v i adc1pwd sr ? adc_1 consumption in power down mode ???50a i adc1run sr ? adc_1 consumption in running mode ???6ma f adc1 sr ? adc_1 analog frequency v dd = 3.3 v 3.33 ? 20 + 4% mhz v dd = 5 v 3.33 ? 32 + 4% t adc1_pu sr ? adc_1 power up delay ??? 1.5 s t adc1_s cc t sample time 4 vdd = 3.3 v f adc1 = 20 mhz, adc1_conf_sample_input = 12 600 ? ? ns sample time 4 vdd = 5.0 v f adc1 = 32 mhz, adc1_conf_sample_input = 17 500 ? ? sample time 4 vdd = 3.3 v f adc1 = 3.33 mhz, adc1_conf_sample_input = 255 ? ? 76.2 s sample time 4 vdd = 5.0 v f adc1 = 3.33 mhz, adc1_conf_sample_input = 255 ??76.2 t adc1_c cc p conversion time 5 vdd = 3.3 v f adc1 = 20mhz, adc1_conf_comp = 0 2.4 ? ? s conversion time 5 vdd = 5.0 v f adc 1 = 32 mhz, adc1_conf_comp = 0 1.5 ? ? s conversion time 5 vdd = 3.3 v f adc 1 = 13.33 mhz, adc1_conf_comp = 0 ??3.6 s conversion time 5 vdd = 5.0 v f adc1 = 13.33 mhz, adc1_conf_comp = 0 ??3.6 s ? adc1_sys sr ? adc_1 digital clock duty cycle adclksel = 1 6 45 ?55 % c s cc d adc_1 input sampling capacitance ? ? ?5 pf c p1 cc d adc_1 input pin capacitance 1 ? ? ?3 pf c p2 cc d adc_1 input pin capacitance 2 ? ? ?1 pf c p3 cc d adc_1 input pin capacitance 3 ? ? ?1.5 pf r sw1 cc d internal resistance of analog source ???1 k ? r sw2 cc d internal resistance of analog source ???2 k ? r ad cc d internal resistance of analog source ???0.3 k ? table 42. adc_1 conversion characteristics (12-bit adc_1) (continued) symbol c parameter conditions 1 value unit min typ max MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 75 i inj sr ? input current injection current injection on one adc_1 input, different from the converted one v dd = 3.3 v 10% ?5 ? 5 ma v dd = 5.0 v 10% ?5 ? 5 inlp cc t absolute integral non-linearity-precise channels no overload ? 1 3 lsb inlx cc t absolute integral non-linearity-extended channels no overload ? 1.5 5 lsb dnl cc t absolute differential non-linearity no overload ? 0.5 1 lsb ofs cc t absolute offset error ??2? lsb gne cc t absolute gain error ??2? lsb tuep 7 cc p total unadjusted error for precise channels, input only pins without current injection ?6 ? 6 lsb t with current injection ?8 ? 8 tuex 7 cc t total unadjusted error for extended channel without current injection ?10 ? 10 lsb t with current injection ?12 ? 12 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified 2 analog and digital v ss must be common (to be tied together externally). 3 v ainx may exceed v ss_adc1 and v dd_adc1 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0xfff. 4 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capac itance to reach its final voltage level within t adc1_s . after the end of the sample time t adc1_s , changes of the analog input voltage have no ef fect on the conversion result. values for the sample clock t adc1_s depend on programming. 5 this parameter does not include the sample time t adc1_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. 6 duty cycle is ensured by using system clock without pres caling. when adclksel = 0, th e duty cycle is ensured by internal divider by 2. 7 total unadjusted error: the maximum e rror that occurs without adjusting offse t and gain errors. this error is a combination of offset, gain and integral linearity errors. table 42. adc_1 conversion characteristics (12-bit adc_1) (continued) symbol c parameter conditions 1 value unit min typ max MPC5606BK microcontroller data sheet, rev. 3 76 freescale semiconductor 3.18 on-chip peripherals 3.18.1 current consumption table 43. on-chip peripherals current consumption 1 symbol c parameter conditions value unit typ i dd_bv(can) cc t can (flexcan) supply current on v dd_bv bit rate = 500 kb/s total (static + dynamic) consumption: ? flexcan in loop-back mode ? xtal at 8 mhz used as can engine clock source ? message sending period is 580 s 8 * f periph + 85 a bit rate = 125 kb/s 8 * f periph + 27 i dd_bv(emios) cc t emios supply current on v dd_bv static consumption: ? emios channel off ? global prescaler enabled 29 * f periph dynamic consumption: ? it does not change varying the frequency (0.003 ma) 3 i dd_bv(sci) cc t sci (linflex) supply current on v dd_bv total (static + dynamic) consumption: ? lin mode ? baud rate: 20 kb/s 5 * f periph + 31 i dd_bv(spi) cc t spi (dspi) supply current on v dd_bv ballast static consumption (only clocked) 1 ballast dynamic consumption (continuous communication): ? baud rate: 2 mb/s ? transmission every 8 s ? frame: 16 bits 16 * f periph i dd_bv (adc_0/adc_1) cc t adc_0/adc_1 supply current on v dd_bv v dd = 5.5 v ballast static consumption (no conversion) 41 * f periph a v dd = 5.5 v ballast dynamic consumption (continuous conversion) 46 * f periph i dd_hv_adc0 cc t adc_0 supply current on v dd_hv_adc0 v dd = 5.5 v analog static consumption (no conversion) 200 v dd = 5.5 v analog dynamic consumption (continuous conversion) 3ma MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 77 i dd_hv_adc1 cc t adc_1 supply current on v dd_hv_adc1 v dd = 5.5 v analog static consumption (no conversion) 300 * f periph a v dd = 5.5 v analog dynamic consumption (continuous conversion) 4ma i dd_hv(flash) cc t cflash + dflash supply current on v dd_hv v dd = 5.5 v ? 12 ma i dd_bv(pll) cc t pll supply current on v dd_bv v dd = 5.5 v ? 2.5 ma 1 operating conditions: t a = 25 c, f periph = 8 mhz to 64 mhz table 43. on-chip peripherals current consumption 1 (continued) symbol c parameter conditions value unit typ MPC5606BK microcontroller data sheet, rev. 3 electrical characteristics freescale semiconductor 78 3.18.2 dspi characteristics table 44. dspi characteristics 1 no. symbol c parameter dspi0/dspi1/dspi5/ dspi6 dspi2/dspi4 unit min typ max min typ max 1t sck sr d sck cycle time master mode (mtfe = 0) 125 ? ? 333 2 ??ns dslave mode (mtfe = 0) 125 ? ? 333 ? ? d master mode (mtfe = 1) 83 ? ? 125 ? ? dslave mode (mtfe = 1) 83 ? ? 125 ? ? ?f dspi sr d dspi digital controller frequency ? ? f cpu ??f cpu mhz 2t cscext 3 sr d cs to sck delay slave mode 32 ? ? 32 ? ? ns 3t ascext 4 sr d after sck delay slave mode 1/f dspi + 5 ? ? 1/f dspi + 5 ? ? ns 4t sdc cc d sck duty cycle master mode ? t sck /2 ? ? t sck /2 ? ns sr d slave mode t sck /2 ? ? t sck /2 ? ? 5t a sr d slave access time slave mode ? ? 1/f dspi + 70 ? ? 1/f dspi + 130 ns 6t di sr d slave sout disable time slave mode 7 ? ? 7 ? ? ns 7t pcsc cc d pcs x to pcss time ? 13 5 ?? 13 5 ?? 8t pasc cc d pcss to pcs x time ? 13 5 ?? 13 5 ?? 9t sui sr d data setup time for inputs master mode 43 ? ? 145 ? ? ns slave mode 5 ? ? 5 ? ? 10 t hi sr d data hold time for inputs master mode 0 ? ? 0 ? ? ns slave mode 2 6 ?? 2 6 ?? 11 t suo 7 cc d data valid after sck edge master mode ? ? 32 ? ? 50 ns slave mode ? ? 52 ? ? 160 12 t ho 7 cc d data hold time for outputs master mode 0 ? ? 0 ? ? ns slave mode 8 ? ? 13 ? ? electrical characteristics MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 79 figure 23. dspi classic spi timing ? master, cpha = 0 1 operating conditions: c out = 10 to 50 pf, slew in = 3.5 to 15 ns. 2 for dspi4, if sout is mapped to a slow pad while sck is mapped to a medium pad (or vice versa), the minimum cycle time for sck should be calculated based on the rise and fall times of the slow pad. for mtfe=1, sout must not be mapped to a slow pad while sck is mapped to a medium pad. 3 the t csc delay value is configurable thr ough a register. when configuring t csc (using pcssck and cssck fields in dspi_ctar x registers), delay between internal cs and internal sck must be higher than ? t csc to ensure positive t cscext . 4 the t asc delay value is configurable through a register. when configuring t asc (using pasc and asc fields in dspi_ctar x registers), delay between internal cs and internal sck must be higher than ? t asc to ensure positive t ascext . 5 for dspi x _ctar n [pcssck] = 11. 6 this delay value corresponds to smpl_pt = 00b wh ich is bit field 9 and 8 of dspi_mcr register. 7 sck and sout are configured as medium pad. data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers shown reference ta b l e 4 4 . MPC5606BK microcontroller data sheet, rev. 3 80 freescale semiconductor figure 24. dspi classic spi timing ? master, cpha = 1 figure 25. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 81 figure 26. dspi classic spi timing ? slave, cpha = 1 figure 27. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . MPC5606BK microcontroller data sheet, rev. 3 82 freescale semiconductor figure 28. dspi modified transfer format timing ? master, cpha = 1 figure 29. dspi modified transfer format timing ? slave, cpha = 0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 note: numbers shown reference ta b l e 4 4 . MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 83 figure 30. dspi modified transfer format timing ? slave, cpha = 1 figure 31. dspi pcs strobe (pcss ) timing 3.18.3 jtag characteristics table 45. jtag characteristics no. symbol c parameter value unit min typ max 1t jcyc cc d tck cycle time 64 ? ? ns 2t tdis cc d tdi setup time 15 ? ? ns 3t tdih cc d tdi hold time 5 ? ? ns 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 4 . pcsx 7 8 pcss note: numbers shown reference ta bl e 4 4 . MPC5606BK microcontroller data sheet, rev. 3 84 freescale semiconductor figure 32. timing diagram ? jtag boundary scan 4t tmss cc d tms setup time 15 ? ? ns 5t tmsh cc d tms hold time 5 ? ? ns 6t tdov cc d tck low to tdo valid ? ? 33 ns 7t tdoi cc d tck low to tdo invalid 6 ? ? ns table 45. jtag characteristics (continued) no. symbol c parameter value unit min typ max input data valid output data valid data inputs data outputs data outputs tck note: numbers shown reference ta bl e 4 5 . 3/5 2/4 7 6 MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 85 4 package characteristics 4.1 package mechanical data 4.1.1 176 lqfp figure 33. 176 lqfp package mechanical drawing (part 1 of 3) MPC5606BK microcontroller data sheet, rev. 3 86 freescale semiconductor figure 34. 176 lqfp package mechanical drawing (part 2 of 3) MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 87 figure 35. 176 lqfp package mechanical drawing (part 3 of 3) MPC5606BK microcontroller data sheet, rev. 3 88 freescale semiconductor 4.1.2 144 lqfp figure 36. 144 lqfp package mechanical drawing (part 1 of 2) MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 89 figure 37. 144 lqfp package mechanical drawing (part 2 of 2) MPC5606BK microcontroller data sheet, rev. 3 90 freescale semiconductor 4.1.3 100 lqfp figure 38. 100 lqfp package mechanical drawing (part 1 of 3) MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 91 figure 39. 100 lqfp package mechanical drawing (part 2 of 3) MPC5606BK microcontroller data sheet, rev. 3 92 freescale semiconductor figure 40. 100 lqfp package mechanical drawing (part 3 of 3) MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 93 5 ordering information figure 41. commercial product code structure qualification status power architecture core automotive platform core version flash memory size (core dependent) product temperature spec. mpc56 b mll6 example code: 06 package code frequency qualification status m = general market qualified s = automotive qualified p = engineering samples automotive platform 56 = power architecture in 90nm core version 0 = e200z0 flash memory size (for z0 core) 5 = 768 kb 6 = 1024 kb product b = body fab and mask indicator k = tsmc fab 0 = version of the maskset a = mask set indicator (blank = 1st production maskset, a = 2nd, b = 3rd, etc) r = tape & reel (blank if tray) r temperature spec. c = ?40 to 85 c v = ?40 to 105 c m = ?40 to 125 c package code ll = 100 lqfp lq = 144 lqfp lu = 176 lqfp frequency 4 = up to 48 mhz 6 = up to 64 mhz fab and mask indicator k0a note: not all options are available on all devices. MPC5606BK microcontroller data sheet, rev. 3 94 freescale semiconductor 6 revision history table 46. revision history revision date description of changes 1 22 apr 2011 initial release. 2 15 may 2013 changed device number to MPC5606BK. in table 2 (functional port pins) , updated pa[11] af2, pd[13] af2, and ph[11] af3 i/o direction to ?i/o?. in table 3 (pad types) , corrected ?fast? in the ?s? row to ?slow.? in table 5 (pad3v5v field description) , updated footnote 2. in table 6 (oscillator_margin field description) , updated footnote 2. inserted section 3.2.3, nvusro[watchdog_en] field description . in table 8 (absolute maximum ratings) , table 9 (recommended operating conditions (3.3 v)) , and table 10 (recommended operating conditions (5.0 v)) , corrected the parameter description for v dd_adc to ?voltage on vdd_hv_adc0, vdd_hv_adc1 (adc reference) with respect to ground (v ss )? in section 3.6.1, i/o pad types bullet item, removed nexus reference. in table 12 (i/o input dc electrical characteristics) , added specifications for 85 c. in table 13 (i/o pull-up/pull-down dc electrical characteristics) , table 14 (slow configuration output buffer electrical characteristics) , table 15 (medium configuration output buffer electrical characteristics) , and table 16 (fast configuration output buffer electrical characteristics) , changed sentence in footnote 2 to ?all pads but reset are configured in input or in high impedance state.? in table 15 (medium configuration output buffer electrical characteristics) , for v ol , changed i oh to i ol . updated table 20 (i/o weight) . in table 21 (reset electrical characteristics) changed sentence in footnote 4 to ?all pads but reset are configured in input or in high impedance state.? in table 22 (voltage regulator electrical characteristics) , corrected the maximum value for i dd_bv in table 22 (voltage regulator electrical characteristics) to 300 ma. in table 23 (low voltage monitor electrical characteristics) , changed v porup classification tag from ?p? (production testing guaranteed) to ?d? (design simulation). changed v lvdhv3bh classification tag from ?p? (production testin g guaranteed) to ?t? (design characterization). in table 23 (low voltage monitor electrical characteristics) , changed v lv d h v 3 l , v lvdhv3bl minimums from 2.7 v to 2.6 v. MPC5606BK microcontroller data sheet, rev. 3 freescale semiconductor 95 2 (cont.) 15 may 2013 in table 24 (electrical characteristics in different application modes) , ? changed i ddmax typ to 81 ma and i ddmax typ to 130 ma. ? changed i ddrun typ for fcpu = 32 mhz to 40 ma. ? changed i ddrun typ for fcpu = 48 mhz to 54 ma. added i ddrun max of 96 ma. ? changed i ddrun typ for fcpu = 64 mhz to 67 ma. added i ddrun max of 120 ma. ? changed i ddhalt at t a = 25 c typ to 10 ma and i ddhalt max to 15 ma. ? changed i ddhalt at t a = 125 c typ to 15 ma and i ddhalt max to 28 ma. ? changed i ddstop t a temperature from ?40 c to 25 c. ? changed i ddstop at t a = 25 c typ to 130 a and i ddstop max to 500 a. ? changed i ddstop at t a = 55 c typ to 180 a. ? changed i ddstop at t a = 85 c typ to 1 ma and i ddstop max to 5 ma. ? changed i ddstop at t a = 105 c typ to 3 ma and i ddstop max to 9 ma. ? changed i ddstop at t a = 125 c typ to 5 ma and i ddstop max to 14 ma. ? changed i ddstdby2 at t a = 25 c typ to 17 a and max to 80 a. ? changed i ddstdby2 at t a = 55 c typ to 30 a. ? changed i ddstdby2 at t a = 85 c typ to 100 a. ? changed i ddstdby2 at t a = 105 c typ to 280 a and max to 950 a. ? changed i ddstdby2 at t a = 125 c typ to 460 a and max to 1700 a. ? changed the parameter classification for i ddstandby2 (t a = 125 c) ? changed i ddstdby1 at t a = 25 c typ to 12 a and max to 50 a. ? changed i ddstdby1 at t a = 55 c typ to 24 a. ? changed i ddstdby1 at t a = 85 c typ to 48 a. ? changed i ddstdby1 at t a = 105 c typ to 150 a and max to 500 a. ? changed i ddstdby1 at t a = 125 c typ to 260 a. ? changed the third sentence of footnote 3 to begin with ?the given value is thought to be a worst case value (64 mhz at 125 c) with all peripherals running.? ? removed footnotes 8 and 9 regarding i ddhalt and i ddstop . ? corrected ?c? characteristics to reflect testing status. in section 3.10, flash memory electrical characteristics , removed the "flash_biu settings vs. frequency of operation" table. in table 28 (flash power supply dc electrical characteristics) , corrected footnote 2 to specify 125 c. in section 3.14, fmpll electrical characteristics , changed the text ?the main oscillator driver? to ?the fxosc or firc sources.? in table 40 (adc input leakage current) , added specifications for 85 c. in table 44 (dspi characteristics) , added t sck specifications for mtfe=1. in table 44 (dspi characteristics) , updated specifications 7 and 8 to 13 ns, all dspis. in adc section, corrected equation 11 . in figure 41 (commercial product code structure) , added ? note: not all options are available on all devices.? removed section 6, abbreviations. 3 24 sep 2013 updated the temperature in table note 2 in table 1 (MPC5606BK family comparison) from 105 o c to 125 o c. table 46. revision history (continued) revision date description of changes how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com rohs-compliant and/or pb- free versions of freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb- free counterparts. for further information, see http://www.freescale.com or contact yo ur freescale sales representative. for information on freescale.s environmental products program, go to http://www.freescale.com/epp. information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2011?2013. all rights reserved. mpc5606b rev. 3 9/2013 |
Price & Availability of MPC5606BK
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |